INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4220/1
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: 24mA (A port)
Balanced Output Drivers: 12mA (B port)
IDT74ALVC162525
3.3V CMOS 18-BIT REGIS-
TERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
B
1
CE
C1
1D
1
0
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
OEBA
54
A
1
SEL
OEAB
CLKE NAB
CLKE NBA
CLK 2BA
CLK 1BA
CL
K AB
55
30
29
28
1
2
27
56
1 of 18 Channels
3
To 17 O ther Channels
DESCRIPTION:
This 18-bit registered bus transceiver is built using advanced dual metal
CMOS technology. Data flow in each direction is controlled by output-enable
(
OEAB and OEBA) and clock-enable (CLKENAB and CLKENBA) inputs. For
the A-to-B data flow, the data flows through a single register. The B-to-A data
can flow through a four-stage pipeline register path, or through a single register
path, depending on the state of the select (
SEL) input. Data is stored in the internal
registers on the low-to-high transition of the clock (CLK) input, provided that the
appropriate
CLKEN inputs are low. The A-to-B data transfer is synchronized
to the CLKAB input, and B-to-A data transfer is synchronized with the CLK1BA
and CLK2BA inputs.
The ALVCH162525 has series resistors in the device output structure of the
"B" port which will significantly reduce line noise when used with light loads. This
driver has been designed to drive 12mA at the designated threshold levels.
The "A" port has a 24mA driver.
To ensure the high-impedance state during power up or power down,
OE
should be tied to V
CC
through a pullup resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
The ALVCH162525 has "bus-hold" which retains the inputs' last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
5
7
pF
C
OUT
Output Capacitance
V
OUT
= 0V
7
9
pF
C
OUT
I/O Port Capacitance
V
IN
= 0V
7
9
pF
CAPACITANCE
(T
A
= +25C, F = 1.0MHz)
Symbol
Description
Max
Unit
V
TERM
(2)
Terminal Voltage with Respect to GND
0.5 to +4.6
V
V
TERM
(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
50 to +50
mA
I
IK
Continuous Clamp Current,
50
mA
V
I
< 0 or V
I
> V
CC
I
OK
Continuous Clamp Current, V
O
< 0
50
mA
I
CC
Continuous Current through each
100
mA
I
SS
V
CC
or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
C LKEN AB
OEAB
A
1
GN D
A
2
A
3
V
CC
A
4
A
5
GN D
A
6
A
7
A
8
A
9
GN D
A
10
A
11
V
CC
A
12
A
13
OEBA
A
14
A
15
C LKEN BA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
SEL
B
1
B
2
GN D
B
3
B
4
V
CC
B
5
B
6
GN D
B
7
B
8
B
9
B
10
GN D
B
11
B
12
V
CC
B
13
B
14
GN D
B
15
B
16
GN D
A
16
A
17
25
26
27
28
32
31
30
29
B
18
C LK2BA
A
18
C LK1BA
B
17
C LKAB
PIN DESCRIPTION
Pin Names
Description
CLKAB
Clock Input for the A to B direction
CLK1BA
Clock Input for the B to A pipeline register
CLK2BA
Clock Input for the B to A output register
CLKENBA
Clock Enable for the CLK1BA and CLK2BA clocks (Active LOW)
CLKENAB
Clock Enable for the CLKAB clock (Active LOW)
OEAB
Output Enable for the B port (Active LOW)
OEBA
Output Enable for the A port (Active LOW)
SEL
Select pin for pipelined/non-pipelined mode in the B-to-A direction
(Active LOW)
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
3
B-TO-A STORAGE (
OEBA = L)
Inputs
Outputs
CLKENBA
CLK2BA
CLK1BA
SEL
Bx
Ax
H
X
X
X
X
A
0
(2)
L
X
H
L
L
L
X
H
H
H
L
L
L
L
(3)
L
L
H
H
(3)
FUNCTION TABLE
(1)
A-TO-B STORAGE (
OEAB = L)
Inputs
Outputs
CLKENAB
CLKAB
Ax
Bx
H
X
X
B
0
(2)
L
L
L
L
H
H
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
= LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established
3. Three CLK1BA edges and one CLK2BA edge are needed to propagate data from B
to A when
SEL is low.
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
1.7
--
--
V
V
CC
= 2.7V to 3.6V
2
--
--
V
IL
Input LOW Voltage Level
V
CC
= 2.3V to 2.7V
--
--
0.7
V
V
CC
= 2.7V to 3.6V
--
--
0.8
I
IH
Input HIGH Current
V
CC
= 3.6V
V
I
= V
CC
--
--
5
A
I
IL
Input LOW Current
V
CC
= 3.6V
V
I
= GND
--
--
5
A
I
OZH
High Impedance Output Current
V
CC
= 3.6V
V
O
= V
CC
--
--
10
A
I
OZL
(3-State Output pins)
V
O
= GND
--
--
10
V
IK
Clamp Diode Voltage
V
CC
= 2.3V, I
IN
= 18mA
--
0.7
1.2
V
V
H
Input Hysteresis
V
CC
= 3.3V
--
100
--
mV
I
CCL
Quiescent Power Supply Current
V
CC
= 3.6V
--
0.1
40
A
I
CCH
V
IN
= GND or V
CC
I
CCZ
I
CC
Quiescent Power Supply Current
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
--
--
750
A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 40C to +85C
NOTE:
1.
Typical values are at V
CC
= 3.3V, +25C ambient.
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
BUS-HOLD CHARACTERISTICS
Symbol
Parameter
(1)
Test Conditions
Min.
Typ.
(2)
Max.
Unit
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 3V
V
I
= 2V
75
--
--
A
I
BHL
V
I
= 0.8V
75
--
--
I
BHH
Bus-Hold Input Sustain Current
V
CC
= 2.3V
V
I
= 1.7V
45
--
--
A
I
BHL
V
I
= 0.7V
45
--
--
I
BHHO
Bus-Hold Input Overdrive Current
V
CC
= 3.6V
V
I
= 0 to 3.6V
--
--
500
A
I
BHLO
NOTES:
1.
Pins with Bus-Hold are identified in the pin description.
2.
Typical values are at V
CC
= 3.3V, +25C ambient.
NOTE:
1.
V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS (B PORT)
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 4mA
1.9
--
I
OH
= 6mA
1.7
--
V
CC
= 2.7V
I
OH
= 4mA
2.2
--
I
OH
= 8mA
2
--
V
CC
= 3V
I
OH
= 6mA
2.4
--
I
OH
= 12mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 4mA
--
0.4
I
OL
= 6mA
--
0.55
V
CC
= 2.7V
I
OL
= 4mA
--
0.4
I
OL
= 8mA
--
0.6
V
CC
= 3V
I
OL
= 6mA
--
0.55
I
OL
= 12mA
--
0.8
NOTE:
1.
V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS (A PORT)
Symbol
Parameter
Test Conditions
(1)
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
I
OH
= 0.1mA
V
CC
0.2
--
V
V
CC
= 2.3V
I
OH
= 6mA
2
--
V
CC
= 2.3V
I
OH
= 12mA
1.7
--
V
CC
= 2.7V
2.2
--
V
CC
= 3V
2.4
--
V
CC
= 3V
I
OH
= 24mA
2
--
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
I
OL
= 0.1mA
--
0.2
V
V
CC
= 2.3V
I
OL
= 6mA
--
0.4
I
OL
= 12mA
--
0.7
V
CC
= 2.7V
I
OL
= 12mA
--
0.4
V
CC
= 3V
I
OL
= 24mA
--
0.55
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
5
OPERATING CHARACTERISTICS, T
A
= 25C
V
CC
= 2.5V 0.2V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Typical
Typical
Unit
C
PD
Power Dissipation Capacitance Outputs enabled
C
L
= 0pF, f = 10Mhz
--
160
pF
C
PD
Power Dissipation Capacitance Outputs disabled
--
160
SWITCHING CHARACTERISTICS (FOR A AND B PORTS)
(1)
V
CC
= 2.5V 0.2V
V
CC
= 2.7V
V
CC
= 3.3V 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
MAX
120
--
125
--
150
--
MHz
t
PLH
Propagation Delay
1
5.5
--
5.4
1
4.7
ns
t
PHL
CLKAB to 2Bx
t
PLH
Propagation Delay
1
4.5
--
4.4
1
4.2
ns
t
PHL
CLK2BA to Ax
t
PZH
Output Enable Time
1
6.7
--
6.8
1
5.7
ns
t
PZL
OEAB to Bx
t
PZH
Output Enable Time
1
6.1
--
6.1
1
5.1
ns
t
PZL
OEBA to Ax
t
PHZ
Output Disable Time
1
6.3
--
5.4
1
4.9
ns
t
PLZ
OEAB to Bx
t
PHZ
Output Disable Time
1
6.3
--
5.4
1
4.9
ns
t
PLZ
OEBA to Ax
t
SU
Set-up Time, Ax data before CLKAB
1.3
--
1.3
--
1.3
--
ns
t
SU
Set-up Time, Bx data before CLK2BA
2.1
--
1.8
--
1.7
--
ns
t
SU
Set-up Time, Bx data before CLK1BA
1.3
--
1.2
--
1.1
--
ns
t
SU
Set-up Time,
SEL before CLK2BA
3.3
--
3.3
--
3.3
--
ns
t
SU
Set-up Time,
CLKENAB before CLKAB
2.1
--
1.9
--
1.6
--
ns
t
SU
Set-up Time,
CLKENBA before CLK1BA
2.7
--
2.5
--
2.1
--
ns
t
SU
Set-up Time,
CLKENBA before CLK2BA
2.7
--
2.5
--
2.2
--
ns
t
H
Hold Time, Ax data after CLKAB
0.7
--
0.4
--
0.9
--
ns
t
H
Hold Time, Bx data before CLK2BA
0.4
--
0
--
0.6
--
ns
t
H
Hold Time, Bx data before CLK1BA
0.8
--
0.4
--
1
--
ns
t
H
Hold Time,
SEL before CLK2BA
0
--
0
--
0.1
--
ns
t
H
Hold Time,
CLKENAB before CLKAB
0.1
--
0.3
--
0.3
--
ns
t
H
Hold Time,
CLKENBA before CLK1BA
0
--
0
--
0.1
--
ns
t
H
Hold Time,
CLKENBA before CLK2BA
0
--
0
--
0
--
ns
t
W
Pulse Duration, CLK HIGH or LOW
3.2
--
3.2
--
3
--
ns
t
SK(O)
Output Skew
(2)
--
--
--
--
--
500
ps
NOTES:
1.
See TEST CIRCUITS AND WAVEFORMS. T
A
= 40C to + 85C.
2.
Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500
500
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
V
IH
V
T
V
T
V
IH
V
T
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW -HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SW ITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2ns; t
R
2ns.
Output Skew - t
SK
(
X
)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol
V
CC
(1)
= 3.3V0.3V V
CC
(1)
= 2.7V
V
CC
(2)
= 2.5V0.2V
Unit
V
LOAD
6
6
2 x Vcc
V
V
IH
2.7
2.7
Vcc
V
V
T
1.5
1.5
Vcc
/ 2
V
V
LZ
300
300
150
mV
V
HZ
300
300
150
mV
C
L
50
50
30
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
V
LOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVC162525
3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
7
ORDERING INFORMATION
ID T
XX
ALVC
XXX
XX
Package
Device Type
Temp. R ange
PV
PA
PF
162
74
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
18-Bit Registered Bus Transceiver w ith 3-State Outputs
-40C to +85C
X
XX
Family
Bus-Hold
525
Bus-Hold
Double-Density with Resistors, 12mA (B Port)
24m A (A Port)
H
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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