5v925.PMD
1
INDUSTRIAL TEMPERATURE RANGE
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
SEPTEMBER 2002
2002 Integrated Device Technology, Inc.
DSC-5943/1
c
IDT5V925
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE
CLOCK GENERATOR
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
3V to 3.6V operating voltage
3.125 MHz to 160MHz output frequency range
4 programmable frequency outputs
Input from fundamental crystal oscillator or external source
Balanced Drive Outputs 12mA
PLL disable mode for low frequency testing
Select inputs (S
[1:0]
) for divide selection (multiply ratio of 2,
3, 4, 5, 6, 7, and 8)
5V tolerant inputs
Low output skew/jitter
External PLL feedback, internal loop filter
Available in 16-pin QSOP package
DESCRIPTION:
The IDT5V925 is a high-performance, low skew, low jitter phase-locked
loop (PLL) clock driver. It provides precise phase and frequency alignment
of its clock outputs to an externally applied clock input or internal crystal
oscillator. The IDT5V925 has been specially designed to interface with
Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz
clock from 25MHz input. It can also be programmed to provide output
frequencies ranging from 3.125MHz to 160MHz with input frequencies
ranging from 3.125MHz to 80MHz.
The IDT5V925 includes an internal RC filter that provides excellent jitter
characteristics and eliminates the need for external components. When
using the optional crystal input, the chip accepts a 10-30MHz fundamental
mode crystal with a maximum equivalent series resistance of 50
. The on-
chip crystal oscillator includes the feedback resistor and crystal capacitors
(nominal load capacitance is 15pF).
APPLICATIONS:
Ethernet/fast ethernet
Router
Network switches
SAN
Instrumentation
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
PH ASE
DETEC TO R
F B
C LKIN
X
1
X
2
OPTION AL
C RYST AL
XT AL
OSC
LOO P
FIL TER
VC O
Q /N
Q
0
Q
1
Q
2
0
1
VC O
DIVIDE
1/N
SE LEC T
M OD E
S
0
S
1
O E
2
INDUSTRIAL TEMPERATURE RANGE
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
PIN CONFIGURATION
QSOP
TOP VIEW
Pin Names
I/O
Description
CLKIN
I
Input clock
X
1
(1)
I
Crystal oscillator input. Connected to GND if
oscillator not required.
X
2
(1)
O
Crystal oscillator output. Leave unconnected for
clock input.
FB
I
PLL feedback input which should be connected to
Q/N output pin only. PLL locks onto positive edge
of FB signal.
S
[1:0]
I
Three level divider/mode select pins. Float to MID.
Q
[2:0]
O
Output at N*CLKIN frequency
Q/N
O
Programmable divide-by-N clock output
OE
I
Tri-state output enable. When asserted HIGH, clock
outputs are high impedance.
V
DD
PWR
Power supply for output buffers
GND
PWR
Ground supply for output buffers
V
DDQ
PWR
Power supply for PLL
GNDQ
PWR
Ground supply for PLL
PIN DESCRIPTION
NOTE:
1. For best accuracy, use parallel resonant crystal specified for a load capacitance
of 15pF.
Output Used for
Allowable CLKIN Range (MHz)
(1,2)
Output Frequency Relationships
Feedback
Minimum
Maximum
Q/N
Q
[2:0]
Q/N
25/N
160/N
CLKIN
CLKIN x N
FUNCTION TABLE
NOTES:
1. Operation in the specified CLKIN frequency range guarantees that the VCO will operate in the optimal range of 25MHz to 160MHz. Operation with CLKIN outside specified
frequency ranges may result in invalid or out-of-lock outputs.
2. Q
[2:0
] is not allowed to be used as feedback.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1
S
0
GNDQ
V
DDQ
X
1
X
2
CLKIN
FB
GND
Q
2
Q
1
Q
0
Q/N
GND
OE
V
DD
Symbol
Description
Max
Unit
V
TERM
Supply Voltage to Ground
0.5 to +7
V
DC Output Voltage
V
OUT
0.5 to V
CC
+0.5
V
DC Input Voltage V
IN
0.5 to +7
V
T
A
= 85C
Maximum Power Dissipation
.55
W
T
STG
Storage Temperature
65 to +150
C
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50
maximum equivalent series resonance.
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
DIVIDE SELECTION TABLE
(1)
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Factory Test Mode: operation not specified,
3. Ethernet mode (use a 25MHz input frequency and Q/N as feedback).
4. Test mode for low frequency testing. In this mode, CLKIN bypasses the VCO (VCO powered down). Frequency must be > 1MHz due to dynamic circuits in the frequency
dividers. Q
[2:0]
outputs are divided by 2 in test mode.
S1
S0
Divide-by-N Value
Mode
L
L
FACTORY TEST
(2)
L
M
2
PLL
L
H
3
PLL
M
L
4
PLL
M
M
5
(3)
PLL
M
H
6
PLL
H
L
7
PLL
H
M
8
PLL
H
H
16
TEST
(4)
Symbol
Description
Min.
Typ.
Max.
Unit
V
DD/
V
DDQ
Power Supply Voltage
3
3.3
3.6
V
T
A
Operating Temperature
40
+25
+85
C
C
L
Output Load Capacitance
--
--
15
pF
C
IN
Input Capacitance, CLKIN, FB, OE, F = 1MHz, V
IN
= 0V, T
A
= 25C
--
5
7
pF
OPERATING CONDITIONS
NOTE:
1.
These inputs are normally wired to V
CC
, GND, or unconnected. If the inputs are switched in real time, the function and timing of the outputs may glitch, and the PLL may require
an additional lock time before all the datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Min.
Typ.
(7)
Max
Unit
V
IL
Input LOW Voltage
--
--
0.8
V
V
IH
Input HIGH Voltage
2
--
--
V
V
IHH
(1)
Input HIGH Voltage
3-level input only
V
DD
- 0.6
--
--
V
V
IMM
(1)
Input MID Voltage
3-level input only
V
DD
/2 - 0.3
--
V
DD
/2 + 0.3
V
V
ILL
(1)
Input LOW Voltage
3-level input only
--
--
0.6
V
I
IN
Input Leakage Current
V
IN
= V
DD
or GND, V
DD
= Max
- 5
--
+5
A
(CLKIN, FB Inputs only)
V
IN
= V
DD
HIGH Level
--
--
+200
I
3
3-Level Input DC Current, S
[1:0]
V
IN
= V
DD
/2
MID Level
- 50
--
+50
A
V
IN
= GND
LOW Level
- 200
--
--
I
IH
Input HIGH Current
V
IN
= V
DD
- 5
0.07
+5
A
V
OL
Output LOW Voltage
I
OL
= 12mA
--
0.15
0.55
V
V
OH
Output HIGH Voltage
I
OH
= -12mA
2.4
2.8
--
V
4
INDUSTRIAL TEMPERATURE RANGE
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
R,
t
F
Rise Time, Fall Time
(1)
0.8V to 2V
--
0.7
1.5
ns
d
T
Output/Duty Cycle
(1)
V
T
= V
DD
/2
45
--
55
%
t
PD
CLKIN to FB
(1)
V
T
= V
DD
/2
- 300
--
300
ps
t
SK
Output to Output Skew
(1)
V
T
= V
DD
/2; Q
[2:0]
--
--
100
ps
V
T
= V
DD
/2; Q/N - Q
[2:0]
--
--
300
t
J
Cycle - Cycle Jitter
(1)
--
--
200
ps
f
OUT
Output Frequency
25
--
160
MHz
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
Max
Unit
I
DDQ
Quiescent Supply Current
V
DD
= Max.
--
0.7
2
mA
CLKIN = FB = X
1
= GND
S
[1:0]
= HH
OE = H
All outputs unloaded
I
DD
Supply Current per Input
V
DD
= Max., V
IN
= 3V
--
1
30
A
I
DD
Dynamic Supply Current
V
DD
= 3.6V
--
77
130
mA
S
[1:0]
=LM
OE = GND
F
OUT
= 60MHz
All outputs unloaded
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
NOTE:
1. This parameter is guaranteed by design but not tested.
INPUT TIMING REQUIREMENTS
Symbol
Description
Min.
Max.
Unit
t
R,
t
F
Maximum Input Rise and Fall Time, 0.8V to 2V
(1)
--
2
ns
D
H
Input Duty Cycle
(1)
25
75
%
f
OSC
XTAL Oscillator Frequency
--
30
MHz
f
IN
Input Frequency
25/N
160/N
MHz
NOTE:
1. This parameter is guaranteed by design but not tested.
5
INDUSTRIAL TEMPERATURE RANGE
IDT5V925
PROGRAMMABLE CLOCK GENERATOR
TEST LOADS AND WAVEFORMS
HOW TO USE THE 5V925
The 5V925 is a general-purpose phase-locked loop (PLL) that can be
used as a zero delay buffer or a clock multiplier. It generates three outputs
at the VCO frequency and one output at the VCO frequency divided by n,
where n is determined by the Mode/Frequency Select input pins S
0
and S
1
.
The PLL will adjust the VCO frequency (within the limits of the Function
Table) to ensure that the input frequency equals the Q/N frequency.
The 5V925 can accept two types of input signal. The first is a reference
clock generated by another device on the board which needs to be
reproduced with a minimal delay between the incoming clock and output.
The second is an external crystal. When used in the first mode, the crystal
input (X
1
) should be tied to ground and the crystal output (X
2
) should be left
unconnected.
15pF
150
OUTPUT
V
CC
150
2V
V
T H
= V
C C
/2
0V
1ns
3V
1ns
2V
V
T H
= V
C C
/2
0V
t
R
t
F
V
C C
0.8
0.8
AC Test Load
Input Test Waveform
Output Waveform
F B
CLKIN
X
2
X
1
S
0
S
1
Q /N
Q
0
Q
1
Q
2
5V925
Figure 1
By connecting Q/N to FB (see Figure 1), the 5V925 not only becomes
a zero delay buffer, but also a clock multiplier. With proper selection of S
0
and S
1
, the Q
0
Q
2
outputs will generate two, three, up to eight times the input
clock frequency. Make sure that the input and output frequency specifica-
tions are not violated (refer to Function Table). There are some applications
where higher fan-out is required. These kinds of applications could be
addressed by using the 5V925 in conjunction with a clock buffer such as the
49FCT3805. Figure 2 shows how higher fan-out with different clock rates
can be generated.
Figure 2
5 C O PIES
OF Q /N
5 C O PIES
OF Q
49FC T38 05
F B
C LKIN
X
2
X
1
S
0
S
1
Q
[2:0]
Q/N
IN A
IN B
5V925
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