Integrated
Circuit
Systems, Inc.
ICS91730
0794D--05/23/05
Block Diagram
Pin Configuration
Features:
ICS91730 is a Spread Spectrum Clock targeted for
Mobile PC and LCD panel applications that
generates an EMI-optimized clock signal (EMI peak
reduction of 7-14 dB on 3rd-19th harmonics) through
use of Spread Spectrum techniques.
ICS91730 focuses on the lower input frequency
range of 14.318 to 80.00 MHz with a spread
modulation of 20kHz to 40kHz.
Specifications:
Supply Voltages: V
DD
= 3.3V 0.3V
Frequency range: 14.318 MHz
Fin 80 MHz
Cyc to Cyc jitter: <150ps
Output duty cycle 45-55%
Guarantees +85C operational condition.
8-pin SOIC
Reference input
Low EMI, Spread Modulating, Clock Generator
Functionality
CLK
CL
REFOUT
KOUT
OUT
PD#
PD#
CLKIN
CLKIN
PLL1
PLL1
Spread
Spread
Spectr
Spectrum
um
SD
SDA
AT
TA
A
SCLK
SCLK
FS_IN1
Control
Control
Logic
Logic
Config.
Config.
Reg.
Reg.
FSIN_1
0
-0.8 down spread
1
-1.25 down spread
27.00MHz in --> 27.00MHz out
MHz
Spread % default
14.318 MHz in --> 27MHz out
CLKIN
1
8
PD#*
VDD
2
7
SCLK
GND
3
6
SDATA
CLKOUT
4
5
REF_OUT/FS_IN1*
8 Pin SOIC
* Internal Pull-Up Resistor
2
ICS91730
0794D--05/23/05
Pin Descriptions
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
CLKIN
PWR
Input for reference clock.
2
VDD
IN
Power supply, nominal 3.3V
3
GND
OUT
Ground pin.
4
CLKOUT
I/O
Modulated clock output.
Un-modulated 3.3V reference clock output.
Frequency select latch input. Refer to the functionality table.
6
SDATA
PWR
Data pin for SMBus circuitry, 5V tolerant.
7
SCLK
PWR
Clock pin of SMBus circuitry, 5V tolerant.
8
PD#*
PWR
Asynchronous active low input pin, with 120Kohm internal pull-up resistor,
used to power down the device. The internal clocks are disabled and the
VCO and the crystal are stopped.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
I/O
REF_OUT/FS_IN1*
5
3
ICS91730
0794D--05/23/05
Table 1: Frequency Configuration Table
(See I2C Byte 0)
Above is the hard coded 5 bit (32 entry) ROM table.
FS3:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from
FS_IN1 latched input hardware pins.
FS_IN1
FS4. Upon power-up the default is to use hardware selection of FS_IN1 latched value.
FS3 = 0, FS2
= 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).
To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power
up default of FS_IN1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software
selection by switching this bit to a `1' and then program the desired percentage by changing byte0 bits 7:3.
FS4
FS3
FS2
FS1
FS0
Sprd Type Sprd %
0
0
0
0
0
0.60
0
0
0
0
1
0.80
0
0
0
1
0
1.00
0
0
0
1
1
1.25
0
0
1
0
0
1.50
0
0
1
0
1
2.00
0
0
1
1
0
0.50
0
0
1
1
1
1.00
0
1
0
0
0
0.60
0
1
0
0
1
1.00
0
1
0
1
0
0.80
0
1
0
1
1
CTR SPD
0.3
0
1
1
0
0
1.50
0
1
1
0
1
1.75
0
1
1
1
0
2.00
0
1
1
1
1
2.50
1
0
0
0
0
3.00
1
0
0
0
1
1.25
1
0
0
1
0
0.40
1
0
0
1
1
0.50
1
0
1
0
0
0.70
1
0
1
0
1
1.00
1
0
1
1
0
1.20
1
0
1
1
1
1.50
1
1
0
0
0
0.60
1
1
0
0
1
0.80
1
1
0
1
0
1.00
1
1
0
1
1
1.25
1
1
1
0
0
1.50
1
1
1
0
1
2.00
1
1
1
1
0
0.50
1
1
1
1
1
1.00
48in/48out
66in/66out
DOWN
SPREAD
(-)
CENTER SPD
(+/-)
14in/27out
DOWN
SPREAD
(-)
CENTER SPD
(+/-)
14in/14out
27in/27out
CENTER SPD
(+/-)
DOWN
SPREAD
(-)
DOWN
SPREAD
(-)
4
ICS91730
0794D--05/23/05
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address D4
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address D5
(H)
Index Block Read Operation
Slave Address D4
(H)
Beginning Byte = N
ACK
ACK
5
ICS91730
0794D--05/23/05
Byte
0
Pin #
Name
Control Function
0
1
PWD
Bit 7
-
FS0
Spread/FS0
RW
1
Bit 6
-
FS1
Spread/FS1
RW
0
Bit 5
FS2
Spread/FS2
RW
0
Bit 4
FS3
Spread/FS3
RW
0
Bit 3
FS4
FS4
RW
0
Bit 2
PD# Tri_Sate
PD# Tri_Sate
RW
Hi-Z
LOW
1
Bit 1
Spread Enable
Spread Enable
RW
OFF
ON
1
Bit 0
HW/SW Control
Spread Spectrum Control
FS 3:4 Hard/Software
Select
RW
HW
SW
0
Byte
1
Pin #
Name
Control Function
0
1
PWD
Bit 7
REF_OUT
REF_OUT_Enable
RW
Disable
Enable
1
Bit 6
-
REF_OUT
Slew Rate REF-OUT
RW
Nominal
Fast
1
Bit 5
FS-IN_1
FS-IN_1 Readback
R
-
-
X
Bit 4
(Reserved)
(Reserved)
R
-
-
0
Bit 3
CLK_OUT
Slew Rate CLK-OUT
RW
Nominal
Fast
1
Bit 2
CLK_OUT
CLK_OUT_Enable
RW
Disable
Enable
1
Bit 1
(Reserved)
(Reserved)
R
-
-
1
Bit 0
(Reserved)
(Reserved)
R
-
-
1
Byte
2
Pin #
Name
Control Function
0
1
PWD
Bit 7
x
-
(Reserved)
-
-
-
1
Bit 6
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Bit 5
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Bit 4
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Bit 3
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Bit 2
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Bit 1
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Bit 0
x
(Reserved)
(Reserved)
RW
Disable
Enable
1
Affected Pin
Affected Pin
Affected Pin
Srpead Pecentage
See Table1
These are I2C bits
only
Type
Bit Control
Type
Bit Control
Type
Bit Control
PDF 
ZIP