Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- OE TIming Diagram
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Termination for 3.3V LVPECL Outputs
- Differential Clock Input Interface
- LVPECL Clock Input Interface
- Thernal Release Path
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Cout
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8534-01 is a low skew, 1-to-22 Differen-
tial-to-3.3V LVPECL Fanout Buffer and a member
of the HiPerClockSTM Family of High Performance
Clock Solutions from ICS. The ICS8534-01 has two
selectable clock inputs. The CLK, nCLK pair can
accept most standard differential input levels. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The de-
vice is internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the OE
pin. The ICS8534-01's low output and part-to-part skew char-
acteristics make it ideal for workstation, server, and other high
performance clock distribution applications.
F
EATURES
22 differential LVPECL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Output skew: 100ps (maximum)
Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Additive phase jitter, RMS: 0.04ps (typical)
3.3V supply mode
0C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
ICS
CLK
nCLK
PCLK
nPCLK
Q0:Q21
nQ0:nQ21
LE
Q
D
CLK_SEL
OE
0
1
22
22
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ICS8534-01
V
CCO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
V
CCO
V
CCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
V
CCO
nQ13
Q13
nQ12
Q12
nQ11
Q11
nQ10
Q10
nQ9
Q9
nQ8
Q8
nQ7
Q7
V
CCO
V
CCO
nc
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
OE
nc
nc
nQ21
Q21
V
CCO
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
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8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
2. P
IN
C
HARACTERISTICS
l
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Enabled
Disabled
F
IGURE
1. OE T
IMING
D
IAGRAM
nCLK, nPCLK
CLK, PCLK
OE
nQ0:nQ21
Q0:Q21
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
=0C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
=0C
TO
85C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
=0C
TO
85C
l
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
22.3C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
=0C
TO
85C
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
=0C
TO
85C
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O
N
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter, RMS
@ 156.25MHz (12KHz - 20MHz)
= 0.04ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
8534AY-01
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REV. A NOVEMBER 19, 2004
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Integrated
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ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
t
sk(o)
nQx
Qx
nQy
nQy
P
ART
-
TO
-P
ART
S
KEW
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
nQx
LVPECL
V
CMR
Cross Points
V
PP
V
CC
V
EE
nCLK, nPCLK
CLK, PCLK
-1.3V 0.165V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ21
Q0:Q21
P
ROPAGATION
D
ELAY
nCLK, nPCLK
CLK, PCLK
nQ0:nQ21
Q0:Q21
t
PD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
2V
V
CC
,
V
CCO
V
EE
8534AY-01
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REV. A NOVEMBER 19, 2004
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Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
8534AY-01
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REV. A NOVEMBER 19, 2004
9
Integrated
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Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
IGURE
4C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4A to 4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
4A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
4E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8534AY-01
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REV. A NOVEMBER 19, 2004
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ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
SWING
and V
OH
must meet the V
PP
and V
CMR
input requirements.
Figures 5A to 5F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
F
IGURE
5A.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
O
PEN
C
OLLECTOR
CML D
RIVER
F
IGURE
5B. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
B
UILT
-I
N
P
ULLUP
CML D
RIVER
F
IGURE
5C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
5F.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
5E.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PC L K /n PC LK
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
F
IGURE
5D. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
8534AY-01
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REV. A NOVEMBER 19, 2004
11
Integrated
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Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
EXPOSED PAD
Expose Metal Pad
(GROUND PAD)
GROUND PLANE
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
THERM AL VIA
SOLDER M ASK
F
IGURE
6. P.C. B
OARD
FOR
E
XPOSED
P
AD
T
HERMAL
R
ELEASE
P
ATH
E
XAMPLE
T
HERMAL
R
ELEASE
P
ATH
The exposed metal pad provides heat transfer from the device
to the P.C. board. The exposed metal pad is ground pad con-
nected to ground plane through thermal via. The exposed pad
on the device to the exposed metal pad on the PCB is con-
tacted through solder as shown in
Figure 6. For further informa-
tion, please refer to the Application Note on Surface Mount As-
sembly of Amkor's Thermally /Electrically Enhance Leadframe
Base Package, Amkor Technology.
8534AY-01
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REV. A NOVEMBER 19, 2004
12
Integrated
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Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8534-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8534-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 230mA = 796.95mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 22 * 30mW = 660mW
Total Power
_MAX
(3.465V, with all outputs switching) = 797mW + 660mW = 1457mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 1.457W * 17.2C/W = 110.1C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3C/W
17.2C/W
15.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
64-P
IN
TQFP, E-P
AD
, F
ORCED
C
ONVECTION
8534AY-01
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REV. A NOVEMBER 19, 2004
13
Integrated
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Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 7.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
7. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8534AY-01
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REV. A NOVEMBER 19, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8534-01 is: 1474
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
64 L
EAD
TQFP, E-P
AD
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3C/W
17.2C/W
15.1C/W
8534AY-01
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REV. A NOVEMBER 19, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
64 L
EAD
TQFP, E-P
AD
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
D
H
-
D
C
A
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
4
6
A
-
-
-
-
0
2
.
1
1
A
5
0
.
0
0
1
.
0
5
1
.
0
2
A
5
9
.
0
0
.
1
5
0
.
1
b
7
1
.
0
2
2
.
0
7
2
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
2
1
1
D
C
I
S
A
B
0
0
.
0
1
2
D
.
f
e
R
0
5
.
7
E
C
I
S
A
B
0
0
.
2
1
1
E
C
I
S
A
B
0
0
.
0
1
2
E
.
f
e
R
0
5
.
7
e
C
I
S
A
B
0
5
.
0
L
5
4
.
0
0
6
.
0
5
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www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
16
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
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10. O
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
17
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
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