8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8533-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
G
ENERAL
D
ESCRIPTION
The ICS8533-01 is a low skew, high perfor-
mance 1-to-4 Differential-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockSTM family
of High Performance Clock Solutions from ICS.
The ICS8533-01 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, CML,
or SSTL input levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8533-01 ideal for those applications demanding
well defined performance and repeatability.
F
EATURES
4 differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, HSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency up to 650MHz
Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.4ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ3
Q0 - Q3
Enabled
Disabled
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8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
=3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these condition or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
=3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
=3.3V5%, T
A
= 0C
TO
70C
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8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
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8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
PARAMETER MEASUREMENT INFORMATION
F
IGURE
2 - O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2.0V
V
CC
F
IGURE
4 - O
UTPUT
S
KEW
tsk(o)
Qx
nQx
Qy
nQy
F
IGURE
3 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
CLK, PCLK
nCLK, nPCLK
V
EE
V
CC
V
EE
= -1.3V 0.135V
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
F
IGURE
5 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
F
IGURE
7 - odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK, PCLK, Qx
nCLK, nPCLK, nQx
F
IGURE
6 - P
ROPAGATION
D
ELAY
t
PD
CLK, PCLK
nCLK, nPCLK
Q0 - Q3
nQ0 - nQ3
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
F
IGURE
8: S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 8 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~
V
CC
/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible
to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the
input voltage swing. For example, if the input clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8XXX.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8XXX is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 50mA = 173.3mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.294W * 66.6C/W = 89.6C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance
q
JA
for 20-pin TSSOP, Forced Convection
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 8.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
Using V
CC_MAX
= 3.465, this results in V
OH_MAX
= 2.465V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
Using V
CC_MAX
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50
] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50
] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
9 - LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8533-01 is: 404
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-153
L
O
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8533AG-01
www.icst.com/products/hiperclocks.html
REV. B JULY 16, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8533-01
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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