8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8531-01 is a low skew, high performance
1-to-9 Differential-to-3.3V LVPECL Fanout Buffer
a n d a m e m b e r o f t h e H i P e r C l o c k S TM
family of High Performance Clock Solutions from
ICS. The ICS8531-01 has two selectable clock
inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the out-
puts during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output skew and part-to-part skew characteris-
tics make the ICS8531-01 ideal for high performance work-
station and server applications.
HiPerClockSTM
,&6
F
EATURES
9 differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency up to 500MHz
Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 2ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
32 31 30 29 28 27 26 25
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
CCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
CCO
ICS8531-01
Vcco
Q6
nQ6
Q7
nQ7
Q8
nQ8
Vcco
V
CCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
D
Q
LE
CLK_EN
CLK_SEL
0
1
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
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F
IGURE
1: CLK_EN T
IMING
D
IAGRAM
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ8
Q0 - Q8
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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C
:
2
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T
O
N
H
I
.
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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T
:
4
E
T
O
N
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
2 - O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2.0V
V
CCO
= 2.0V
V
CC
V
CCO
V
EE
= -1.3V
0.135V
F
IGURE
3 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
CLK, PCLK
nCLK, nPCLK
V
EE
V
CC
F
IGURE
4 - O
UTPUT
S
KEW
tsk(o)
Qx
nQx
Qy
nQy
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
IGURE
5 - P
ART
-
TO
-P
ART
S
KEW
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
F
IGURE
6 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
F
IGURE
7 - P
ROPAGATION
D
ELAY
t
PD
CLK, PCLK
nCLK, nPCLK
Q0 - Q8
nQ0 - nQ8
F
IGURE
8 - odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK, PCLK, Qx
nCLK, nPCLK, nQx
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
F
IGURE
9: S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8531-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 70mA = 242.6mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30.2mW = 271.8mW
Total Power
_MAX
(3.465V, with all outputs switching) = 242.6mW + 271.8mW = 514.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.514W * 42.1C/W = 91.6C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance
q
JA
for 32-pin LQFP Forced Convection
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 10.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
Using V
CC_MAX
= 3.465, this results in V
OH_MAX
= 2.465V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
Using V
CC_MAX
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50
] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50
] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
F
IGURE
10 - LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8531-01 is: 632
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs.
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
AND
D
IMENSIONS
- Y S
UFFIX
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8531AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 9, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8531-01
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
t
n
u
o
C
e
r
u
t
a
r
e
p
m
e
T
1
0
-
Y
A
1
3
5
8
S
C
I
1
0
-
Y
A
1
3
5
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
y
a
r
t
r
e
p
0
5
2
C
0
7
o
t
C
0
T
1
0
-
Y
A
1
3
5
8
S
C
I
1
0
-
Y
A
1
3
5
8
S
C
I
l
e
e
R
d
n
a
e
p
a
T
n
o
P
F
Q
L
d
a
e
L
2
3
0
0
0
1
C
0
7
o
t
C
0
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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