85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
1
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS85314-01 is a low skew, high performance
1-to-5 Differential-to-3.3V LVPECL fanout buffer
and a member of the HiPerClockSTM family of
High Performance Clock Solutions from ICS.
The ICS85314-01 has two selectable clock inputs.
The CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85314-01 ideal for those applications demanding well
defined performance and repeatability.
F
EATURES
5 differential 2.5V/3.3V LVPECL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 400ps (maximum)
Propagation delay: CLK0, nCLK0 - 2.1ns (maximum)
CLK1 - 2.1ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40C to 85C ambient operating temperature
Compatible to part number MC100LVEL14
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
nCLK_EN
V
CC
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
V
EE
HiPerClockSTM
,&6
ICS85314-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
ICS85314-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
CLK0
nCLK0
CLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
nCLK_EN
CLK_SEL
D
Q
LE
0
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
2
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
3
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
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3B. C
LOCK
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NPUT
F
UNCTION
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F
IGURE
1 - nCLK_EN T
IMING
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IAGRAM
Enabled
Disabled
nCLK0
CLK0, CLK1
nCLK_EN
nQ0:nQ4
Q0:Q4
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
4
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
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I
.
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
5
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V, V
EE
= 0V, T
A
= -40C
TO
85C
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V
2
-
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
6
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
SCOPE
Qx
nQx
LVPECL
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
CC
O
UTPUT
L
OAD
T
EST
C
IRCUIT
V
CC
= 2V
V
EE
=
-1.8V to -0.375V
D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
nCLK
CLK
V
EE
V
CC
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
7
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
O
UTPUT
S
KEW
tsk(o)
nQx
Qx
nQy
Qy
P
ROPAGATION
D
ELAY
(D
IFFERENTIAL
I
NPUT
)
t
PD
nCLK
CLK
nQ0:nQ4
Q0:Q4
P
ROPAGATION
D
ELAY
(LVCMOS I
NPUT
)
t
PD
V
CC
2
nQ0:nQ4
Q0:Q4
SCLK
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
8
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
Clock Inputs
and Outputs
20%
80%
80%
20%
t
R
t
F
V
S W I N G
I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ4
Q0:Q4
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
9
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
2 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
F
IGURE
3B - LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A - LVPECL O
UTPUT
T
ERMINATION
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
10
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85314-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 55mA = 209mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power
_MAX
(3.465V, with all outputs switching) = 209mW + 151mW = 360mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.360W * 66.6C/W = 109C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6A. T
HERMAL
R
ESISTANCE
q
JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6B. T
HERMAL
R
ESISTANCE
q
JA
FOR
20-
PIN
SOIC, F
ORCED
C
ONVECTION
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
11
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
(V
CC_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
4 - LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
12
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85314-01 is: 674
T
ABLE
7A.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
TSSOP
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7B.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
SOIC
q
JA
by Velocity (Linear Feet per Minute)
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
13
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
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85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
14
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
B
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Y
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s
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85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
15
Integrated
Circuit
Systems, Inc.
ICS85314-01
L
OW
S
KEW
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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