ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
1
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
G
ENERAL
D
ESCRIPTION
The ICS85311 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V ECL/
LVPECL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input levels.T h e
ICS85311 is characterized to operate from either a 2.5V
or a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS85311 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
F
EATURES
2 differential 2.5V/3.3V LVPECL / ECL outputs
1 CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency up to 1GHz
Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
Output skew: 15ps (maximum)
Part-to-part skew: 100ps (maximum)
Propagation delay: 1.4ns (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.465V
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85311
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockSTM
,&6
Vcc
CLK
nCLK
V
EE
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
2
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
3
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
112C/W
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
3B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
4
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
T
ABLE
4F. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, V
CC
= 2.5V5%, T
A
= 0C
TO
70C
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3D. D
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HARACTERISTICS
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3E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, V
CC
= 2.5V5%, T
A
= 0C
TO
70C
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ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
5
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
1A - 3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2.0V
V
CC
V
EE
= -1.3V
0.135V
F
IGURE
1B - 2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
= 2.0V
V
CC
V
EE
= -0.5V
0.125V
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
6
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
F
IGURE
4 - P
ART
-
TO
-P
ART
S
KEW
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
F
IGURE
3 - O
UTPUT
S
KEW
tsk(o)
Qx
nQx
Qy
nQy
F
IGURE
2 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
CLK
nCLK
V
EE
V
CC
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
7
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
F
IGURE
7 - odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK, Qx
nCLK, nQx
F
IGURE
6 - P
ROPAGATION
D
ELAY
t
PD
CLK
nCLK
Q0 - Q1
nQ0 - nQ1
F
IGURE
5 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
8
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
F
IGURE
8 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
9
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85311.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation of the ICS85311 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core) = V
CC
* I
EE
= 3.465V * 25mA = 86.6mW
Power (outputs) = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 x 30.2mW = 60.4mW
Total Power (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the
reliability of the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125
C.
In order to determine if the junction temperature is below 125
C, the appropriate junction-to-ambient thermal
resistance
JA
must be used
in conjunction with the total power dissipation. Assuming a moderate air low of 200 linear
feet per minute and a multi-layer board, the appropriate value is 103.3
C/W per the table below:
Tj =
JA
* Pd_total + T
A
where Pd_total is the total power dissipation of the device and T
A
is the ambient
temperature. Therefore, Tj for an ambient temperature of 70
C with all outputs switching is:
70
C + 0.147W * 103.3
C/W = 85.2
C. This is well below the limit of 125
C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are
loaded, supply voltage, air flow, and the type of board (single layer or multi-layer).
Thermal Resistance q
JA
for 8-pin SOIC, Forced Convection
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 153.3
C/W
128.5
C/W
115.5
C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7
C/W
103.3
C/W
97.1
C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
10
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 9.
To calculate worst case power dissipation into the load, use the following equations which assume a 50
load,
and a termination voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC
- 2V))/R
L
]*(V
CC
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
(V
CC
- 2V))/R
L
]*(V
CC
- V
OL_MAX
)
For logic high , V
OUT
= V
OH_MAX
= V
CC
1.0V
Using V
CC
= 3.465, this results in V
OH_MAX
= 2.465V
For logic low , V
OUT
= V
OL_MAX
= V
CC
1.7V
Using V
CC
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50
]*(3.465V - 2.465V) = 20.0mW
Pd_L = [(1.765V - (3.465V - 2V))/50
]*(3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
Figure 9 - LVPECL Driver Circuit and Termination
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
11
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS85311 is: 225
T
ABLE
5.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 153.3
C/W
128.5
C/W
115.5
C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7
C/W
103.3
C/W
97.1
C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
12
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
P
ACKAGE
O
UTLINE
- M S
UFFIX
D
E
H
SEATING
PLANE
e
A
N
A1
A2
B
C
L
4
1
5
8
hx45
.10 (.004)
T
ABLE
6. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
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ICS85311AM
www.icst.com/products/hiperclocks.html
REV. A JUNE 29, 2001
13
Integrated
Circuit
Systems, Inc.
ICS85311
Low Skew, 1-to-2
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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