8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8525 is a low skew, high performance
1-to-4 LVCMOS-to-LVHSTL fanout buffer and a
member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS8525 has two selectable clock inputs that ac-
cept LVCMOS or LVTTL input levels and translate them to
1.8V LVHSTL levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8525 ideal for those applications demanding
well defined performance and repeatability.
F
EATURES
4 differential 1.8V LVHSTL outputs
Selectable LVCMOS / LVTTL clock inputs for redundant
and multiple frequency fanout applications
Maximum output frequency up to 266MHz
Translates LVCMOS and LVTTL levels to 1.8V
LVHSTL levels
Output skew: 35ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 1.9ns (maximum)
3.3V core, 1.8V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
,&6
ICS8525
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
CLK0
CLK1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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I
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1
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G
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F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
Enabled
Disabled
CLK0, CLK1
CLK_EN
nQ0 - nQ3
Q0 - Q3
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8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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T
ABLE
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HARACTERISTICS
,
V
DD
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DDO
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A
= 0C
TO
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4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
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r
r
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C
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l
p
p
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S
r
e
w
o
P
0
5
A
m
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= 0C
TO
70C
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8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
F
IGURE
2 - O
UTPUT
L
OAD
T
EST
C
IRCUIT
PARAMETER MEASUREMENT INFORMATION
F
IGURE
3 - O
UTPUT
S
KEW
SCOPE
LVHSTL
Qx
nQx
V
DD
V
DDO
V
DD =
3.3V 5%
tsk(o)
Qx
nQx
Qy
nQy
V
DDO =
1.8V 0.2V
GND = 0V
Qx
nQx
Qy
nQy
PART 1
PART 2
tsk(pp)
F
IGURE
4 - P
ART
-
TO
-P
ART
S
KEW
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
F
IGURE
6 - P
ROPAGATION
D
ELAY
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
F
IGURE
5 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
F
IGURE
7 - odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK0, CLK 1, Qx
nQx
t
PD
CLK0, CLK1
Q0 - Q3
nQ0 - nQ3
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8525.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8525 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 50mA = 173.25mW
Power (outputs)
MAX
= 32mW/Loaded Output pair
If all outputs are loaded, the total power is 4 x 32mW = 128mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.25mW + 128mW = 301.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.301W * 66.6C/W = 90.05C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance
q
JA
for 20-pin TSSOP, Forced Convection
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in
Figure 8.
To calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a
termination voltage of V
DD
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
DD_MAX
1.2V
For logic low, V
OUT
= V
OL_MAX
= V
DD_MAX
0.4V
Pd_H = (1.2V/50
) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
F
IGURE
8 - LVHSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
DDO
R L
50
V
DDO
- 2V
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8525 is: 484
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95, MO-153
L
O
B
M
Y
S
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0
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a
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-
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0
1
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0
8525BG
www.icst.com/products/hiperclocks.html
REV. B JULY 27, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8525
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVHSTL F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
<
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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