Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Function Description
- Frequency Margin Function Table
- Serial Load Operations
- Pin Descriptions
- Pin Characteristics
- OE Control Input Function Table
- SEL Control Input Function Table
- Mode Control Input Function Table
- Serial Mode Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVDS 3.3V DC Characteristics
- LVDS 3.3V/2.5V DC Characteristics
- Crystal Characteristics
- Input Frequency Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input Pins
- 3.3V, 2.5V LVDS Driver Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
1
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS844101I-312 is a low phase-noise
frequency margining synthesizer and is a mem-
ber of the HiPerClock STM family of high perfor-
mance clock solutions from ICS. In the default
mode, the device nominally generates a
312.5MHz LVDS output clock signal from a 25MHz crystal
input. There is also a frequency margining mode available
where the device can be programmed, using the serial in-
terface, to vary the output frequency up or down from nomi-
nal in 2% steps. The ICS844101I-312 is provided in a 16-
pin TSSOP.
F
EATURES
One 312.5MHz nominal LVDS output
Selectable crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal or LVCMOS single-ended
input
Output frequency can be varied in 2% steps from nominal
VCO range: 560MHz - 690MHz
RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.52ps (typical)
Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-complaint
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
GND
S_LOAD
S_DATA
S_CLOCK
SEL
OE
V
DDA
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE
V
DDO
Q
nQ
GND
CLK
XTAL_OUT
XTAL_IN
ICS844101I-312
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
B
LOCK
D
IAGRAM
1
1
0
Phase
Detector
VCO
560 - 690MHz
M
OSC
N
P
Serial Control
Q
nQ
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
O E
CLK
SEL
S_CLOCK
S_DATA
S_LOAD
MODE
XTAL_IN
XTAL_OUT
Pulldown
25MHz
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
2
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
F
UNCTIONAL
D
ESCRIPTION
The ICS844101I-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscilla-
tor is fed into the pre-divider. In frequency margining mode,
the 25MHz crystal frequency is divided by 2 and a 12.5MHz
reference frequency is applied to the phase detector. The
VCO of the PLL operates over a range of 560MHz to
690MHz. The output of the M divider is also applied to the
phase detector.
The default mode for the ICS844101I-312 is 312.5MHz
output frequency using a 25MHz crystal. The output fre-
quency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
quency by adjusting the VCO control voltage. Note that for
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency is
provided in Table 1. When changing back from frequency
margining mode to nominal mode, the device will return to
the default nominal configuration that will provide
312.5MHz output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by sam-
pling the S_DATA bits with the rising edge of S_CLOCK.
After shifting in the 6-bit M divider value, S_LOAD is
transitioned from HIGH to LOW which latches the contents of
the shift-register into the M divider control register. When
S_LOAD is LOW, any transitions of S_CLOCK or S_DATA
are ignored.
L
A
T
X
)
z
H
M
(
r
e
d
i
v
i
D
-
e
r
P
)
P
(
e
c
n
e
r
e
f
e
R
)
z
H
M
(
y
c
n
e
u
q
e
r
F
k
c
a
b
d
e
e
F
)
M
(
r
e
d
i
v
i
D
a
t
a
D
-
M
)
y
r
a
n
i
B
(
O
C
V
)
z
H
M
(
t
u
p
t
u
O
)
N
(
r
e
d
i
v
i
D
t
u
p
t
u
O
)
z
H
M
(
y
c
n
e
u
q
e
r
F
%
e
g
n
a
h
C
5
2
2
5
.
2
1
5
4
1
0
1
1
0
1
5
.
2
6
5
2
5
2
.
1
8
2
0
.
0
1
-
5
2
2
5
.
2
1
6
4
0
1
1
1
0
1
5
7
5
2
5
.
7
8
2
0
.
8
-
5
2
2
5
.
2
1
7
4
1
1
1
1
0
1
5
.
7
8
5
2
5
7
.
3
9
2
0
.
6
-
5
2
2
5
.
2
1
8
4
0
0
0
0
1
1
0
0
6
2
0
0
3
0
.
4
-
5
2
2
5
.
2
1
9
4
1
0
0
0
1
1
5
.
2
1
6
2
5
2
.
6
0
3
0
.
2
-
5
2
2
5
.
2
1
0
5
0
1
0
0
1
1
5
2
6
2
5
.
2
1
3
0
5
2
2
5
.
2
1
1
5
1
1
0
0
1
1
5
.
7
3
6
2
5
7
.
8
1
3
0
.
2
5
2
2
5
.
2
1
2
5
0
0
1
0
1
1
0
5
6
2
5
2
3
0
.
4
5
2
2
5
.
2
1
3
5
1
0
1
0
1
1
5
.
2
6
6
2
5
2
.
1
3
3
0
.
6
5
2
2
5
.
2
1
4
5
0
1
1
0
1
1
5
7
6
2
5
.
7
3
3
0
.
8
5
2
2
5
.
2
1
5
5
1
1
1
0
1
1
5
.
7
8
6
2
5
7
.
3
4
3
0
.
0
1
T
ABLE
1. F
REQUENCY
M
ARGIN
F
UNCTION
T
ABLE
F
IGURE
1. S
ERIAL
L
OAD
O
PERATIONS
Time
S
ERIAL
L
OADING
t
S
t
H
M5
M4
M3
M2
M1
M0
t
S
S_CLOCK
S_DATA
S_LOAD
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
3
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
2. P
IN
D
ESCRIPTIONS
T
ABLE
3. P
IN
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
2
1
,
1
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
s
r
e
w
o
P
2
D
A
O
L
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
l
a
i
r
e
S
e
h
t
f
o
n
o
i
t
a
r
e
p
o
e
h
t
s
l
o
r
t
n
o
C
3
A
T
A
D
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
e
h
t
n
o
d
e
l
p
m
a
s
a
t
a
D
.
t
u
p
n
i
l
a
i
r
e
s
r
e
t
s
i
g
e
r
t
f
i
h
S
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
4
K
C
O
L
C
_
S
t
u
p
n
I
n
w
o
d
ll
u
P
e
h
t
n
o
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
o
t
n
i
t
u
p
n
i
A
T
A
D
_
S
t
a
t
n
e
s
e
r
p
a
t
a
d
l
a
i
r
e
s
n
i
k
c
o
l
C
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
5
L
E
S
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
K
L
C
s
t
c
e
l
e
s
,
H
G
I
H
n
e
h
W
.
n
i
p
t
c
e
l
e
S
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
n
i
L
A
T
X
s
t
c
e
l
e
s
,
W
O
L
n
e
h
W
6
E
O
t
u
p
n
I
p
u
ll
u
P
.
s
t
u
p
t
u
o
Q
n
/
Q
f
o
g
n
il
b
a
s
i
d
d
n
a
g
n
il
b
a
n
e
s
l
o
r
t
n
o
C
.
n
i
p
e
l
b
a
n
e
t
u
p
t
u
O
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
7
V
A
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
8
V
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
r
o
C
0
1
,
9
,
N
I
_
L
A
T
X
T
U
O
_
L
A
T
X
t
u
p
n
I
e
h
t
s
i
N
I
_
L
A
T
X
,
t
u
p
t
u
o
e
h
t
s
i
T
U
O
_
L
A
T
X
.
e
c
a
f
r
e
t
n
i
l
a
t
s
y
r
c
t
n
a
n
o
s
e
r
l
e
ll
a
r
a
P
.
t
u
p
n
i
1
1
K
L
C
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
L
T
T
V
L
/
S
O
M
C
V
L
4
1
,
3
1
Q
,
Q
n
t
u
p
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
C
E
P
V
L
.
r
i
a
p
t
u
p
t
u
o
l
a
i
t
n
e
r
e
f
f
i
D
5
1
V
O
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
t
u
p
t
u
O
6
1
E
D
O
M
t
u
p
n
I
n
w
o
d
ll
u
P
.
e
d
o
m
g
n
i
n
i
g
r
a
m
y
c
n
e
u
q
e
r
f
=
H
G
I
H
.
e
d
o
m
t
l
u
a
f
e
d
=
W
O
L
.
n
i
p
E
D
O
M
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
:
E
T
O
N
n
w
o
d
ll
u
P
d
n
a
p
u
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
4
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
4D. S
ERIAL
M
ODE
F
UNCTION
T
ABLE
T
ABLE
4A. OE C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
4B. SEL C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
4C. M
ODE
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
t
u
p
n
I
s
t
u
p
t
u
O
E
O
Q
n
,
Q
0
Z
i
H
1
d
e
l
b
a
n
E
t
u
p
n
I
n
o
i
t
i
d
n
o
C
e
d
o
M
Q
n
,
Q
0
e
d
o
M
t
l
u
a
f
e
D
1
e
d
o
M
g
n
i
n
i
g
r
a
M
y
c
n
e
u
q
e
r
F
s
t
u
p
n
I
s
n
o
i
t
i
d
n
o
C
D
A
O
L
_
S
K
C
O
L
C
_
S
A
T
A
D
_
S
L
X
X
.
d
e
r
o
n
g
i
e
r
a
s
t
u
p
n
i
l
a
i
r
e
S
H
a
t
a
D
.
e
d
o
m
t
u
p
n
i
l
a
i
r
e
S
.
K
C
O
L
C
_
S
f
o
e
g
d
e
g
n
i
s
i
r
h
c
a
e
n
o
A
T
A
D
_
S
n
o
a
t
a
d
h
t
i
w
d
e
d
a
o
l
s
i
r
e
t
s
i
g
e
r
t
f
i
h
S
L
X
.
d
e
h
c
t
a
l
e
r
a
r
e
t
s
i
g
e
r
t
f
i
h
s
e
h
t
f
o
s
t
n
e
t
n
o
C
W
O
L
=
L
:
E
T
O
N
H
G
I
H
=
H
e
r
a
c
t
'
n
o
D
=
X
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
i
s
i
R
=
n
o
i
t
i
s
n
a
r
t
e
g
d
e
g
n
il
l
a
F
=
t
u
p
n
I
L
E
S
e
c
r
u
o
S
d
e
t
c
e
l
e
S
0
T
U
O
_
L
A
T
X
,
N
I
_
L
A
T
X
1
K
L
C
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
5
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
8
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
7
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
9
1
A
m
T
ABLE
5B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%,V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
8
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
7
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
8
1
A
m
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
6
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
5C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
T
A
= -40C
TO
85C
T
ABLE
5E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
5D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
6. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
n
o
i
t
a
ll
i
c
s
O
f
o
e
d
o
M
l
a
t
n
e
m
a
d
n
u
F
y
c
n
e
u
q
e
r
F
5
2
z
H
M
)
R
S
E
(
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
5
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
7
F
p
l
e
v
e
L
e
v
i
r
D
0
0
1
W
.
l
a
t
s
y
r
c
t
n
a
n
o
s
e
r
l
e
ll
a
r
a
p
F
p
8
1
n
a
g
n
i
s
u
d
e
z
i
r
e
t
c
a
r
a
h
C
:
E
T
O
N
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
V
D
D
V
3
.
3
=
2
V
C
C
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
V
D
D
V
3
.
3
=
3
.
0
-
8
.
0
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
,
L
E
S
,
K
L
C
,
K
C
O
L
C
_
S
,
D
A
O
L
_
S
E
D
O
M
,
A
T
A
D
_
S
V
D
D
V
=
N
I
5
6
4
.
3
=
0
5
1
A
E
O
V
D
D
V
=
N
I
5
6
4
.
3
=
5
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
,
L
E
S
,
K
L
C
,
K
C
O
L
C
_
S
,
D
A
O
L
_
S
E
D
O
M
,
A
T
A
D
_
S
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
E
O
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
/tv
n
o
i
t
s
i
s
n
a
r
T
t
u
p
n
I
e
t
a
R
ll
a
F
/
e
s
i
R
,
K
C
O
L
C
_
S
,
L
E
S
,
E
O
,
D
A
O
L
_
S
,
A
T
A
D
_
S
E
D
O
M
0
2
v
/
s
n
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
O
e
g
a
t
l
o
V
t
u
p
t
u
O
l
a
i
t
n
e
r
e
f
f
i
D
5
7
3
V
m
V
D
O
V
D
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
4
V
m
V
S
O
e
g
a
t
l
o
V
t
e
s
f
f
O
2
4
.
1
V
V
S
O
V
S
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
5
V
m
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
O
e
g
a
t
l
o
V
t
u
p
t
u
O
l
a
i
t
n
e
r
e
f
f
i
D
5
6
3
V
m
V
D
O
V
D
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
4
V
m
V
S
O
e
g
a
t
l
o
V
t
e
s
f
f
O
7
3
.
1
V
V
S
O
V
S
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
0
5
V
m
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
7
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
8A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
7. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
N
I
t
u
p
n
I
y
c
n
e
u
q
e
r
F
K
L
C
5
2
z
H
M
T
U
O
_
L
A
T
X
/
N
I
_
L
A
T
X
5
2
z
H
M
K
C
O
L
C
_
S
0
5
z
H
M
T
ABLE
8B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%,V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
5
.
2
1
3
z
H
M
t
)
(
t
ij
1
E
T
O
N
;
r
e
t
t
i
J
e
s
a
h
P
S
M
R
W
O
L
=
e
d
o
M
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
,
z
H
M
5
.
2
1
3
2
5
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
6
3
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
t
S
e
m
i
T
p
u
t
e
S
o
t
A
T
A
D
_
S
K
C
O
L
C
_
S
0
1
s
n
K
C
O
L
C
_
S
D
A
O
L
_
S
o
t
0
1
s
n
t
H
e
m
i
T
d
l
o
H
o
t
A
T
A
D
_
S
K
C
O
L
C
_
S
0
1
s
n
.
l
a
t
s
y
r
c
z
H
M
5
2
a
g
n
i
s
u
d
e
z
i
r
e
t
c
a
r
a
h
C
:
1
E
T
O
N
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
5
.
2
1
3
z
H
M
t
)
(
t
ij
1
E
T
O
N
;
r
e
t
t
i
J
e
s
a
h
P
S
M
R
W
O
L
=
e
d
o
M
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
,
z
H
M
5
.
2
1
3
0
5
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
5
7
3
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
t
S
e
m
i
T
p
u
t
e
S
o
t
A
T
A
D
_
S
K
C
O
L
C
_
S
0
1
s
n
K
C
O
L
C
_
S
D
A
O
L
_
S
o
t
0
1
s
n
t
H
e
m
i
T
d
l
o
H
o
t
A
T
A
D
_
S
K
C
O
L
C
_
S
0
1
s
n
.
l
a
t
s
y
r
c
z
H
M
5
2
a
g
n
i
s
u
d
e
z
i
r
e
t
c
a
r
a
h
C
:
1
E
T
O
N
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
8
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q
RMS P
HASE
J
ITTER
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
nQ
O
UTPUT
R
ISE
/F
ALL
T
IME
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
FFSET
V
OLTAGE
S
ETUP
SCOPE
Qx
nQx
LVDS
Power Supply
+
-
Float GND
3.3V
Qx
nQx
3.3V
2.5V
Float GND
+ +
POWER
SUPPLY
SCOPE
LVDS
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
9
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844101I-312 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 3
below were determined using a 25MHz, 18pF
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error.
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844101I-312 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
DD
, V
DDA
, and
V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
. The 10
resis-
tor can also be replaced by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
10
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
3.3V, 2.5V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
F
IGURE
4. T
YPICAL
LVDS D
RIVER
T
ERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
P
INS
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
2.5V or 3.3V
+
-
VDD
100 Ohm Differential Transmission Line
R1
100
LVDS_Driv er
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
11
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844101I-312 is: 4093
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
12
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
6
1
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
4
0
1
.
5
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
13
Integrated
Circuit
Systems, Inc.
ICS844101I-312
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-LVDS
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical
medical instruments.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
2
1
3
-
I
G
A
1
0
1
4
4
8
S
C
I
D
B
T
P
O
S
S
T
d
a
e
L
6
1
e
b
u
t
C
5
8
o
t
C
0
4
-
T
2
1
3
-
I
G
A
1
0
1
4
4
8
S
C
I
D
B
T
P
O
S
S
T
d
a
e
L
6
1
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
F
L
2
1
3
-
I
G
A
1
0
1
4
4
8
S
C
I
D
B
T
P
O
S
S
T
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
6
1
e
b
u
t
C
5
8
o
t
C
0
4
-
T
F
L
2
1
3
-
I
G
A
1
0
1
4
4
8
S
C
I
D
B
T
P
O
S
S
T
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
6
1
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
.
t
n
i
a
l
p
m
o
c
S
H
o
R
e
r
a
d
n
a
n
o
i
t
a
r
u
g
i
f
n
o
c
e
e
r
F
-
b
P
e
h
t
e
r
a
r
e
b
m
u
n
t
r
a
p
e
h
t
o
t
x
i
f
f
u
s
"
F
L
"
n
a
h
t
i
w
d
e
r
e
d
r
o
e
r
a
t
a
h
t
s
t
r
a
P
:
E
T
O
N
PDF 
ZIP