Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- 3.3V LVDS DC Characteristics
- 2.5V LVDS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 2.5V Core/2.5V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Propagation Delay Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Offset Voltage Setup Diagram
- Differential Output Voltage Setup Diagram
- Application Information
- Power Supply Fitlering Techniques
- Crystal Input Interface
- 3.3V, 2.5V LVDS Driver Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
1
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS844004I-01 is a 4 output LVDS Synthesizer
optimized to generate Ethernet reference clock
frequencies and is a member of the HiPerClocks
TM
family of high performance clock solutions from
ICS. Using a 25MHz 18pF parallel resonant crystal,
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and
62.5MHz. The ICS844004I-01 uses ICS' 3
rd
generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844004I-01 is packaged in a small 24-
pin TSSOP package.
F
EATURES
Four LVDS outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
Full 3.3V or 2.5V supply modes
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
1
1
0
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
M = 25 (fixed)
F_SEL[1:0]
0 0 4
0 1 5
1 0 10
1 1 not used
2
OSC
ICS844004I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
DD
o
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
DDO
Q3
nQ3
GND
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DD
nXTAL_SEL
TEST_CLK
GND
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XTAL_OUT
24
23
22
21
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19
18
17
16
15
14
13
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ABLE
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Q2
nQ2
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Pulldown
Pulldown
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
2
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
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844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
3
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = -40C
TO
85C
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%
OR
2.5V5%, TA = -40C
TO
85C
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, TA = -40C
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m
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
4
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
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HARACTERISTICS
,
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DD
= V
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= V
DDO
= 3.3V5%, TA = -40C
TO
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T
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3E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, TA = -40C
TO
85C
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m
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
5
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, TA = -40C
TO
85C
l
o
b
m
y
S
r
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t
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m
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P
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844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
6
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Q0:Q3
t
PD
TEST_CLK
RMS P
HASE
J
ITTER
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQ0:nQ3
tsk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q3
nQ0:nQ3
P
ROPAGATION
D
ELAY
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
SCOPE
Qx
nQx
LVDS
2.5V5%
POWER SUPPLY
+
-
Float GND
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
7
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
O
FFSET
V
OLTAGE
S
ETUP
O
UTPUT
R
ISE
/F
ALL
T
IME
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
8
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844004I-01 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS844004I-01
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844004I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
9
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3.3V, 2.5V LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 3. In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100
across near
F
IGURE
3. T
YPICAL
LVDS D
RIVER
T
ERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
+
-
VDD
100 Ohm Differential Transmission Line
R1
100
LVDS_Driv er
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
10
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844004I-01 is: 2914
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
11
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
12
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockSTM and F
EMTO
C
LOCKS
TM are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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