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84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS84327 is a Crystal-to-3.3V LVPECL
Clock Synthesizer/Fanout Buffer designed for
SONET, 10 Gigabit Fibre Channel and 10 Giga-
bit Ethernet applications and is a member of the
HiperClockS family of High Performance Clock
Solutions from ICS. The output frequency can be set using
the frequency select pins and a 19.44MHz crystal for SONET
frequencies, or a 25MHz crystal for 10 Gigabit Ethernet fre-
quencies, or a 25.5MHz crystal for a 10 Gigabit Fibre Chan-
nel. The low phase noise characteristics of the ICS84327 make
it an ideal clock for these demanding applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 LVPECL outputs
Crystal oscillator interface
Output frequency range: 77.76MHz to 625MHz
Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
RMS phase jitter at 155.52MHz, using a 19.44MHz crystal
(12KHz to 20MHz): 3.4ps (typical)
Phase noise:
Offset
Noise Power
100Hz .................. -92 dBc/Hz
1KHz ................ -105 dBc/Hz
10KHz ................ -122 dBc/Hz
100KHz ................ -123 dBc/Hz
Full 3.3V or 3.3V core, 2.5V output supply mode
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
Q0:Q5
ICS84327
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
V
CCO
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
F_SEL2
V
CCA
V
CC
PLL_SEL
V
EE
V
CCO
PLL
6
/
Feedback
Divider
OSC
6
/
Output
Divider
0
1
XTAL1
XTAL2
F_SEL2
PLL_SEL
MR
F_SEL0
nQ0:nQ5
24
23
22
21
20
19
18
17
16
15
14
13
F_SEL1
F
UNCTION
T
ABLE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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1
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
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D
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T
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84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
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p
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S
g
o
l
a
n
A
0
2
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
50C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
T
ABLE
6A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
6B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V5%, V
CCO
= 2.5V5%, T
A
= 0C
TO
70C
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84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
19.44MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.4ps (typical)
25MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.2ps (typical)
622.08MHz
311.04MHz
155.52MHz
77.76MHz
625MHz
312.5MHz
156.25MHz
78.125MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
O
FFSET
F
REQUENCY
(H
Z
)
P
HASE
N
OISE
(
dBc
)
H
Z
O
FFSET
F
REQUENCY
(H
Z
)
P
HASE
N
OISE
(
dBc
)
H
Z
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ5
Q0:Q5
tsk(o)
nQx
Qx
nQy
Qy
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
V
CCO
-0.5V 0.125V
2V
V
CC
,
V
CCA
2.8V+0.04V
V
EE
V
CC
,
V
CCA
, V
CCO
V
EE
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84327 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
CC
, V
CCA
and V
CCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required.
Figure 1 illustrates how a 10
resistor along
with a 10
F and a .01
F bypass capacitor should be con-
nected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
(V
OH
+ V
OL
/ V
CC
2) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched impedance
t e c h n i q u e s s h o u l d b e u s e d t o m a x i m i z e o p e r a t i n g
frequency and minimize signal distortion.
Figures 2A and 2B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock
component process variations.
A
PPLICATION
I
NFORMATION
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS84327 has been characterized with 18pF parallel reso-
nant crystals. The capacitor values shown in
Figure 4 below were
Figure 4. C
RYSTAL
I
NPU
t I
NTERFACE
C2
22pF
C1
18pF
25MHz X1
ICS84327
19
20
XTAL2
XTAL1
determined using a 25MHz 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
F
IGURE
5A. ICS84327 S
CHEMATIC
E
XAMPLE
S
CHEMATIC
E
XAMPLE
Figure 5A shows a schematic example of using an ICS84327.
In this example, the input is a 25MHz parallel resonant crystal
with load capacitor CL=18pF. The frequency fine tuning
capacitors C1 and C2 is 22pF and 18pF respectively. This
example also shows logic control input handling. The configu-
ration is set at F_SEL[2:0]=011, therefore, the output frequency
is 625MHz. It is recommended to have one decouple capaci-
tor per power pin. Each decoupling capacitor should be lo-
cated as close as possible to the power pin. The low pass
filter R7, C11 and C16 for clean analog supply should also be
located as close to the V
CCA
pin as possible.
RD3
SP
(U1,13)
Zo = 50
RU2
1K
VCCA
C5
0.1u
(U1,24)
VCC
R4
1K
F_SEL1
C1
22p
C6
0.1u
F_SEL0
VCC=3.3V
RU1
SP
RD2
SP
RD1
1K
X1
25MHz,18pF
+
-
R1
50
VCC
F_SEL2
R5
1K
C2
18p
F_SEL1
VCC
F_SEL0
U1
ICS84327
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
VCCO
VEE
PLL_SEL
VCC
VCCA
F_SEL2
XTAL2
XTAL1
MR
F_SEL1
F_SEL0
VCCO
SP = Spare, Not Installed
RU3
1K
C16
10u
VCC
Zo = 50
F_SEL2
C11
0.1u
C3
0.1u
e.g. F_SEL[2:0]=011
R7
24
(U1,16)
VCC
R2
50
R3
50
84327AM
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REV. A SEPTEMBER 18, 2003
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Integrated
Circuit
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ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS84327
Signals
50 Ohm Traces
VCC
X1
C5
C3
ICS84327
C6
C11
GND
R7
U1
C16
VCCA
C2
Pin1
C1
VIA
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REV. A SEPTEMBER 18, 2003
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Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84327.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84327 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power
_MAX
(3.465V, with all outputs switching) = 485mW + 181mW = 666mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.666W * 43C/W = 98.6C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
T
ABLE
7. T
HERMAL
R
ESISTANCE


JA
FOR
24-P
IN
SOIC, F
ORCED
C
ONVECTION
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84327AM
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REV. A SEPTEMBER 18, 2003
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Integrated
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ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
84327AM
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REV. A SEPTEMBER 18, 2003
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Integrated
Circuit
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ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84327 is: 2804
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
S
OIC


JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50C/W
43C/W
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84327AM
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REV. A SEPTEMBER 18, 2003
14
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
FOR
24 L
EAD
SOIC
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
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84327AM
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REV. A SEPTEMBER 18, 2003
15
Integrated
Circuit
Systems, Inc.
ICS84327
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/I
NTEGRATED
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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