ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8431-11 is a general purpose clock
frequency synthesizer for IA64/32 application and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The VCO
operates at a frequency range of 190MHz to
510MHz providing an output frequency range of 95MHz to
255MHz. The output frequency can be programmed using the
parallel interface, M0 thru M8, to the configuration logic.
Spread spectrum clocking is programmed via the control
inputs SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431-11 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-11 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
XTAL1
XTAL2
M0:M8
PLL
FOUT
nFOUT
16
TEST_I/O
OSC
VCO
2
PHASE
DETECTOR
M
SSC
Control
Logic
Configuration
Logic
nP_LOAD
SSC_CTL0
F
EATURES
Fully integrated PLL
Differential 3.3V LVPECL output
Programmable PLL loop divider for generating a variety of
output frequencies.
Crystal oscillator interface
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
Typical RMS cycle-to-cycle jitter 2.6 ps
LVTTL / LVCMOS control inputs
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
3.3V supply voltage
28 lead SOIC
0C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
SSC_CTL1
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
MR
nc
VDDO
FOUT
nFOUT
VEE
ICS8431-11
28-Lead SOIC
M Package
Top View
HiPerClockSTM
,&6
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
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ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. SSC C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
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ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
4.6V
Inputs
-0.5V to VDD + 0.5V
Outputs
-0.5V to VDDO + 0.5V
Ambient Operating Temperature
0C to 85C
Storage Temperature
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
85C
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ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
6. AC C
HARACTERISTICS
,
VDD = VDDA = VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
85C, 16MH
Z
C
RYSTAL
T
ABLE
5. C
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ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
2 -- C
YCLE
-
TO
-C
YCLE
J
ITTER
FOUT
t
jit(cc) =
t
cycle n
t
cycle n+1
nFOUT
t
cycle n
t
cycle n+1
Clock Inputs
and Outputs
80%
20%
80%
20%
t
rise
t
fall
Vswing
F
IGURE
1 -- I
NPUT
AND
O
UTPUT
S
LEW
R
ATES
F
IGURE
3 -- odc &
tPERIOD
Pulse Width (t
PW
)
t
PERIOD
t
PW
t
PERIOD
odc =
nFOUT
FOUT
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A 16MHz series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over
a range of 190 to 510MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle.
The programmable features of the ICS8431-11 support four output operational modes and a programmable PLL loop divider.
The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and
are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the
data present at M0:M8 is transparent to the M-divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched
into the M-divider and any further changes at the M0:M8 inputs will not be seen by the M-divider until the next LOW transition
on nP_LOAD.
The relationship between the VCO frequency, the crystal frequency and the loop counter/divider is defined as follows:
The M count and the required values of M0:M8 for programming the VCO are shown in
Table 3B, Programmable VCO Frequency
Function Table. The frequency out is defined as follows:
For the ICS8431-11, the output divider equals 2. Valid M values for which the PLL will achieve lock are defined as 190
M
510.
16
M
fVCO =
fxtal x
2
FOUT =
fVCO
=
32
fxtal x M
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
AND
O
SCILLATOR
I
NTERFACE
The ICS8431-11 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
A 16MHz crystal divided by 16 before being sent to the phase
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 25.
Figure 1A shows how to interface with a crystal.
Figures 1A, 1B, and 1C show various crystal parameters
which are recommended only as guidelines. Figure 1A shows
how to interface a capacitor with a parallel resonant crystal.
Figure 1B shows the capacitor value needed for the optimum
PPM performance over various parallel resonant crystals.
Figure 1C shows the recommended tuning capacitance for a
various parallel resonant crystal.
F
IGURE
1A. C
RYSTAL
I
NTERFACE
Optional
XTAL2
(Pin 26, SOIC)
XTAL1
(Pin 25, SOIC)
ICS8431-11
F
IGURE
1B. Recommended tuning capacitance for various parallel
resonant crystals.
F
IGURE
1C. Recommended tuning capacitance for various
parallel resonant crystal.
14.318
15.000
16.667
24.000
19.440
20.000
0
10
20
30
40
50
60
14
15
16
17
18
19
20
21
22
23
24
25
Crystal Frequency (MHz)
S
e
r
i
es
C
apac
itor
, C
1
(
p
F
)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
60
Series Capacitor, C1 (pF)
F
r
equency A
ccur
a
cy (
ppm
)
19.44MHz
16MHz
15.00MHz
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
S
PREAD
S
PECTRUM
Spread-spectrum clocking is a frequency modulation tech-
nique for EMI reduction. When spread-spectrum is enabled, a
30KHz triangle waveform is used with 0.5% down-spread
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.
An example of a triangle frequency modulation profile is shown
in
Figure 2 below. The ramp profile can be expressed as:
Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
Fm = Nominal Modulation Frequency (30KHz)
= Modulation Factor (0.5% down spread)
(1 -
) fnom + 2 fm x
x fnom x t when 0 < t <
,
(1 -
) fnom - 2 fm x
x fnom x t when
< t <
1
2 fm
1
2 fm
1
fm
The ICS8431-11 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock fre-
quency (+0.0% / -0.5%). An example of the amount of down
spread relative to the nominal clock frequency can be seen in
the frequency domain, as shown in
Figure 3. The ratio of this
width to the fundamental frequency is typically 0.4%, and will
not exceed 0.6%. The resulting spectral reduction will be
greater than 7dB, as shown in Figure 3. It is important to note
the ICS8431-11 7dB minimum spectral reduction is the com-
ponent-specific EMI reduction, and will not necessarily be the
same as the system EMI reduction.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431-11 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDI, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, better
power supply isolation is required.
Figure 4 illustrates how a
10
along with a 10
F and a .01
F bypass capacitor should
be connected to each power supply pin.
F
IGURE
3. 200MH
Z
C
LOCK
O
UTPUT
IN
F
REQUENCY
D
OMAIN
(A) S
PREAD
-S
PECTRUM
OFF
(B) S
PREAD
-S
PECTRUM
ON
-
10 dBm
= .4%
B
A
Fnom
(1 -
) Fnom
0.5/fm
1/fm
F
IGURE
2. T
RIANGLE
F
REQUENCY
M
ODULATION
F
IGURE
4. P
OWER
S
UPPLY
F
ILTERING
10
VDDA
10
F
.01
F
3.3V
.01
F
VDD
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
T
ERMINATION
FOR
PECL O
UTPUTS
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/PECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
5B. LVPECL O
UTPUT
T
ERMINATION
3.3V
FOUT
FIN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
Z
o
= 50
Z
o
= 50
F
IGURE
5A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(VOH + VOL / VCC 2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
VCC-2V
FIN
FOUT
Z
o
= 50
Z
o
= 50
F
IGURE
6A. R
ECOMMENDED
S
CHEMATIC
L
AYOUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes.
Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
L
AYOUT
G
UIDELINE
The schematic of the ICS8431-11 layout example used in this layout guideline is shown in
Figure 6A. The ICS8431-11 recommended
PCB board layout for this example is shown in
Figure 6B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
VDD
R1
125
R5
10
R1
50
R3
125
C3
0.01uF
R4
84
IN+
IN-
TL1
Zo = 50 Ohm
VDDA
R3
50
X1
R2
84
VDD
U1
8431-11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
GND
TEST_IO
VDD
GND
nFOUT
FOUT
VDDO
NC
NC
NC
VDDA
NC
NC
nP_LOAD
VDDI
XTAL1
XTAL2
Termination A
IN-
C6
0.01uF
IN+
C1
0.1uF
C4
10uF
R2
50
VDD
TL2
Zo = 50 Ohm
VDD0
Termination
B (not shown
in the layout)
C2
0.1uF
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
F
IGURE
6B. PCB B
OARD
L
AYOUT
F
OR
ICS8431-11
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as
close as possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor
and the power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VDDA shares the same power supply with VDD, insert the RC
filter R5, C3, and C4 in between. Place this RC filter as close to
the VDDA as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
traces should be routed first and should be locked prior to routing
other signals traces.
The traces with 50
transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other termi-
nation scheme can also be used but is not shown in this example.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
26 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
GND
X1
R5
C6
TL2 (50 Ohm)
VDD
Signals
C4
U1
ICS8431-11
R2
TL1 (50 Ohm)
C2
R3
VIA
R1
C1
Close to the input
pins of the
receiver
IN-
C3
R4
IN+
ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95, MS-013, MO-119
D
E
H
.10 (.004)
SEATING
PLANE
e
A
N
A1
A2
B
C
L
14
15
28
1
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C
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S
A
B
0
5
0
.
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H
0
0
.
0
1
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0
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.
0
h
5
2
.
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.
0
0
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ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MH
Z
, L
OW
J
ITTER
,
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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