Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise at 125MHz
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Crystal Input Interface
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Application Schematic
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transitor Count
- Package Outline
- Package Dimensions
- Ordering Information
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
1
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843021I-01 is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS843021I-01 uses a 25MHz crystal to
synthesize 125MHz. The ICS843021I-01 has
excellent phase jitter performance, over the 1.875MHz 20MHz
integration range. The ICS843021I-01 is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limited
board space.
F
EATURES
1 differential 3.3V LVPECL output
Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
Output frequency: 125MHz, using a 25MHz crystal
VCO range: 490MHz - 640MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical) (for 3.3V)
Full 3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
ICS843021I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
V
CC
XTAL_OUT
XTAL_IN
V
EE
1
2
3
4
Q0
nQ0
V
CC
OE
8
7
6
5
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
OSC
Phase
Detector
VCO
4
(fixed)
20
(fixed)
XTAL_IN
XTAL_OUT
Q0
nQ0
25MHz
OE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
2
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
3
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
85C
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%
OR
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A
= -40C
TO
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843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
4
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
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843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
5
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
(3.3V
OR
2.5V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz (3.3V) = 0.41ps (typical)
1.875MHz to 20MHz (2.5V) = 0.42ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Gigabit Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
843021AGI-01
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REV. A NOVEMBER 30, 2004
6
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
RMS P
HASE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.165V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0
nQ0
V
EE
V
CC
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
EE
V
CC
843021AGI-01
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REV. A NOVEMBER 30, 2004
7
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 1. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843021I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
843021AGI-01
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REV. A NOVEMBER 30, 2004
8
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50
to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in
Figure 3C.
F
IGURE
3C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
F
IGURE
3B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
F
IGURE
3A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
Zo = 50 Ohm
R1
250
+
-
2.5V
2,5V LVPECL
Driv er
R4
62.5
R3
250
Zo = 50 Ohm
2.5V
VCC=2.5V
R1
50
R3
18
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
VCC=2.5V
2.5V
R2
50
2,5V LVPECL
Driv er
VCC=2.5V
R1
50
R2
50
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
843021AGI-01
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REV. A NOVEMBER 30, 2004
9
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
S
CHEMATIC
Figure 4 shows an example of ICS843021I-01 application
schematic. In this example, the device is operated at
V
CC
= 3.3V. The decoupling capacitor should be located as
close as possible to the power pin. The input is driven by a
25MHz quartz crystal. For the LVPECL output drivers, only
two termination examples are shown in this schematic.
Additional termination approaches are shown in the LVPECL
Termination Application Note.
F
IGURE
4. ICS843021I-01 S
CHEMATIC
E
XAMPLE
R3
50
Zo = 50
Optional Termination
C4
.1uF
C5
.1uF
VCC = 3.3V
Zo = 50 Ohm
OE
R5
133
X1
25MHz
U1
843021I-01
1
2
3
4
8
7
6
5
VCC
XTAL_OUT
XTAL_IN
VEE
Q0
nQO
Vcc
OE
R3
133
R2
50
R1
50
R4
82.5
C2
27pF
Zo = 50
C1
27pF
R6
82.5
Zo = 50 Ohm
+
-
+
-
VCC
18pF
C3
10uF
3.3V
843021AGI-01
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REV. A NOVEMBER 30, 2004
10
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843021I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843021I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 60mA = 207.9mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 207.9mW + 30mW = 237.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.238W * 90.5C/W = 106.5C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
8-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843021AGI-01
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REV. A NOVEMBER 30, 2004
11
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ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
843021AGI-01
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REV. A NOVEMBER 30, 2004
12
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843021I-01 is: 1765
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
13
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
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m
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8
A
-
-
0
2
.
1
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.
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9
0
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4
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0
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8
a
a
a
-
-
0
1
.
0
843021AGI-01
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REV. A NOVEMBER 30, 2004
14
Integrated
Circuit
Systems, Inc.
ICS843021I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
125MH
Z
LVPECL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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