Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plot @ 125MHz
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- RMS Phase Jitter
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Application Schematic
- Schematic Example
- PC Board Layout Example
- Footprint Table
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
1
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS840021I is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS840021I uses a 25MHz crystal to synthesize
125MHz. The ICS840021I has excellent phase
jitter performance, over the 1.875MHz 20MHz integration
range. The ICS840021I is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
F
EATURES
1 LVCMOS/LVTTL output, 15 output impedence
Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
Output frequency: 125MHz
VCO range: 560MHz to 680MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.48ps (typical) (3.3V)
Offset
Noise Power
100Hz ............... -97.8 dBc/Hz
1kHz .............. -124.6 dBc/Hz
10kHz .............. -132.5 dBc/Hz
100kHz .............. -131.1 dBc/Hz
Voltage supply modes:
V
DD
/V
DDA
= 3.3V
V
DD
/V
DDA
= 2.5V
-40C to 85C ambient operating temperature
Lead-Free package fully RoHS compliant
HiPerClockSTM
ICS
ICS840021I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q0
GND
nc
8
7
6
5
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
OSC
Phase
Detector
VCO
5
25
(fixed)
XTAL_IN
XTAL_OUT
OE
Q0
25MHz
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
2
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
3
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -40C
TO
85C
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AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
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840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
4
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
5. C
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C
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840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
5
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
(3.3V
OR
2.5V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz (3.3V) = 0.48ps (typical)
1.875MHz to 20MHz (2.5V) = 0.50ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Gigabit Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
6
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
RMS P
HASE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
t
PW
Q0
GND
V
DD,
V
DDA
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
SCOPE
Qx
LVCMOS
1.25V 5%
-1.25V 5%
GND
V
DD,
V
DDA
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
7
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840021I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840021I provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 1
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C1
33p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
8
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
PPLICATION
S
CHEMATIC
Figure 3A shows a schematic example of the ICS840021I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 22pF and C2 = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
F
IGURE
3A. ICS840021I S
CHEMATIC
E
XAMPLE
F
IGURE
3B. ICS840021I PC B
OARD
L
AYOUT
E
XAMPLE
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B shows an example of ICS840021I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the
Table 7. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
T
ABLE
7. F
OOTPRINT
T
ABLE
e
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5
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8
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C
,
4
C
3
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,
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s
U1
ICS840021i
1
2
3
4
8
7
6
5
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
NC
C1
22pF
C2
33pF
C4
0.1u
VDDA
R2
10
Q
R3
33
VDD
VDD
VDD=3.3V
OE
X1
LVCMOS
C5
0.1u
C3
10uF
Zo = 50 Ohm
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
9
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840021I is: 1961
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
10
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
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840021AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 19, 2005
11
Integrated
Circuit
Systems, Inc.
ICS840021I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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