Document Outline
- General Description
- Features
- Frequency Select Function Table for Ethernet Frequencies
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
1
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS840004-11 is a 4 output LVCMOS/
LVTTL Synthesizer optimized to generate
Ethernet reference clock frequencies and is a
member of the HiPerClocks
TM
family of high
performance clock solutions from ICS. Using a
25MHz, 18pF parallel resonant crystal, 125MHz and
62.5MHz can be generated based on one frequency select
pin (F_SEL). The ICS840004-11 uses ICS' 3
rd
generation low
phase noise VCO technology and can achieve 1ps or lower
typical random rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS840004-11 is packaged in a small
20-pin TSSOP package.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
F
EATURES
Four LVCMOS/LVTTL outputs, 15
typical output imped-
ance
Crystal oscillator interface
Input frequency range: 22.4MHz to 28MHz
Output frequency Range: 56MHz - 140MHz
VCO Range: 560MHz - 700MHz
RMS phase jitter at 125MHz (1.875MHz - 20MHz):
0.70ps (typical)
RMS phase noise at 125MHz:
Full 3.3V supply
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
Q0
Q1
Q2
Q3
OE
F_SEL
XTAL_IN
XTAL_OUT
OSC
VCO
M = 25 (fixed)
F_SEL
0 10
1 5
N
Phase
Detector
25MHz
Pullup
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
FOR
E
THERNET
F
REQUENCIES
P
IN
A
SSIGNMENT
ICS840004-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
F_SEL
nc
nc
nc
OE
nc
nc
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
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2
1
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
2
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
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Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
3
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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m
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
4
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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E
T
O
N
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
5
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
@3.3V
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
@2.5V
100
1k
10k
100k
1M
10M
100M
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.54ps
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
Raw Phase Noise Data
1Gb Ethernet Filter
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.70ps
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
Raw Phase Noise Data
1Gb Ethernet Filter
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
6
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0:Q3
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
DD
,
V
DDA
, V
DDO
GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
t
sk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
S
KEW
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
7
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840004-11 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840004-11 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 25MHz 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
8
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840004-11 is: 1795
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
9
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
N
0
2
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
4
.
6
0
6
.
6
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MO-153
Integrated
Circuit
Systems, Inc.
840004AG-11
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 3, 2005
10
ICS840004-11
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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