8344
www.icst.com
REV. B FEBRUARY 2, 2001
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8344 is a low voltage, low skew fanout
buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8344 is designed to translate any
differential signal levels to LVCMOS levels. The
low impedance LVCMOS outputs are designed to drive 50
series or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. ICS8344 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
F
EATURES
24 LVCMOS outputs, 7
typical output impedance
Output frequency up to 167MHz
275ps output skew, 600ps part to part skew
Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS without external bias networks
Translates any single-ended input signal to LVCMOS with
resistor bias on nCLK input
Translates and inverts any single-ended input signal to
LVCMOS with resistor bias on CLK input
Multiple differential clock input pairs for redundant clock
applications
LVCMOS control inputs
Multiple output enable pins for disabling unused outputs in
reduced fanout applications
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0C to 70C ambient operating temperature
Industrial temperature versions available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
OE1
OE2
OE3
CLK0
nCLK0
VDDI
GND
CLK1
nCLK1
VDDI
GND
CLK_SEL
Q8
Q9
VDDO
GND
Q10
Q11
Q12
Q13
VDDO
GND
Q14
Q15
0
1
0
1
CLK0
nCLK0
OE1
OE2
OE3
Q0 - Q7
O8 - Q15
O16 - Q23
CLK_SEL
CLK1
nCLK1
48-Lead LQFP
Y Package
Top View
ICS8344
HiPerClockSTM
,&6
8344
www.icst.com
REV. B FEBRUARY 2, 2001
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
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8344
www.icst.com
REV. B FEBRUARY 2, 2001
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
3A. O
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E
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F
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T
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i
c
a
p
a
c
F
.
2
/
I
D
D
V
8344
www.icst.com
REV. B FEBRUARY 2, 2001
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
4.6V
Inputs
-0.5V to VDD + 0.5V
Outputs
-0.5V to VDDO + 0.5V
Ambient Operating Temperature
0C to 70C
Storage Temperature
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of product at these condition or any conditions beyond those listed
in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4C. LVCMOS DC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
70C
l
o
b
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5
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L
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,
5
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3
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H
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5
3
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=
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=
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=
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p
n
i
x
K
L
C
n
,
x
K
L
C
r
o
F
:
E
T
O
N
8344
www.icst.com
REV. B FEBRUARY 2, 2001
5
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
5A. AC E
LECTRICAL
C
HARACTERISTICS
,
VDDI = VDDO = 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
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r
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m
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P
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T
:
5
E
T
O
N
8344
www.icst.com
REV. B FEBRUARY 2, 2001
6
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
4F. LVCMOS DC C
HARACTERISTICS
,
VDDI = 3.3V5%, VDDO = 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4E. D
IFFERENTIAL
DC C
HARACTERISTICS
,
VDDI = 3.3V5%, VDDO = 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
VDDI = 3.3V5%, VDDO = 2.5V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
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P
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5
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5
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=
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5
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m
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=
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r
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F
:
E
T
O
N
8344
www.icst.com
REV. B FEBRUARY 2, 2001
7
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
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T
ABLE
5B. AC E
LECTRICAL
C
HARACTERISTICS
,
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:
5
E
T
O
N
8344
www.icst.com
REV. B FEBRUARY 2, 2001
8
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
4I. LVCMOS DC C
HARACTERISTICS
,
VDDI = VDDO = 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4H. D
IFFERENTIAL
DC C
HARACTERISTICS
,
VDDI = VDDO = 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4G. P
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S
UPPLY
DC C
HARACTERISTICS
,
VDDI = VDDO = 2.5V5%, T
A
= 0C
TO
70C
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,
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K
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C
r
o
F
:
E
T
O
N
8344
www.icst.com
REV. B FEBRUARY 2, 2001
9
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
5C. AC E
LECTRICAL
C
HARACTERISTICS
,
VDDI = VDDO = 2.5V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
e
m
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8344
www.icst.com
REV. B FEBRUARY 2, 2001
10
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
1A, 1B, 1C - I
NPUT
C
LOCK
W
AVEFORMS
VPP
VCMR
CLK
nCLK
GND
VDDI
CROSS POINTS
F
IGURE
1A - LVDS, HSTL D
IFFERENTIAL
I
NPUT
L
EVELS
VPP
VCMR
CLK
nCLK
GND
VDDI
CROSS POINTS
F
IGURE
1B - LVPECL D
IFFERENTIAL
I
NPUT
L
EVEL
GND
VDDI
F
IGURE
1C- LVCMOS
AND
LVTTL S
INGLE
E
NDED
I
NPUT
L
EVEL
CLK
or
nCLK
8344
www.icst.com
REV. B FEBRUARY 2, 2001
11
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
2A, 2B - T
IMING
W
AVEFORMS
VOH - 300mV
VOL + 300mV
tPHZ
tPZH
tPLZ
tPZL
F
IGURE
2B - D
ISABLE
AND
E
NABLE
T
IMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
OEx
OEx
Q
Q
3.3V
0V
VDDO/2
VOH
VOL
VDDO/2
CLK
nCLK
Q
tPHL
tPLH
VDDO/2
VPP
F
IGURE
2A - P
ROPAGATION
D
ELAYS
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
8344
www.icst.com
REV. B FEBRUARY 2, 2001
12
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
3A, 3B- S
KEW
D
EFINITIONS
& W
AVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
nCLK
Q0 - Q7
Q8 - Q15
Q16 - Q23
tsk(o)
tsk(o)
F
IGURE
3B - O
UTPUT
S
KEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
VPP
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
nCLK
Q0, Q8, Q16
Q7, Q15, Q23
tsk(b)
tsk(b)
F
IGURE
3A - B
ANK
S
KEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
VPP
VDDO/2
VDDO/2
VDDO/2
VDDO/2
VDDO/2
VDDO/2
VDDO/2
VDDO/2
8344
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REV. B FEBRUARY 2, 2001
13
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
CLK
nCLK
PART 1 Q0 - Q7
Q8 - Q15
Q16 - Q23
PART 2 Q0 - Q7
Q8 - Q15
Q16 - Q23
tsk(p)
tsk(p)
F
IGURE
4B - O
UTPUT
S
KEW
fin = 167MHz, Vpp = 300mV, tr = tf = 200ps
VPP
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply
voltages and with equal load conditions.
VDDO/2
VDDO/2
VDDO/2
VDDO/2
F
IGURE
4A - S
KEW
D
EFINITIONS
& W
AVEFORMS
8344
www.icst.com
REV. B FEBRUARY 2, 2001
14
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
E
E1
D1
D
ccc C
SEATING
PLANE
D2
-C-
E2
e
A
A1
A2
b
c
L
N
14
26
1
2
3
13
27
39
52
40
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
C
C
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
8
4
A
0
6
.
1
1
A
5
0
.
0
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
7
1
.
0
2
2
.
0
7
2
.
0
c
9
0
.
0
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
0
5
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
0
5
.
5
e
C
I
S
A
B
5
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
7
c
c
c
8
0
.
0
T
ABLE
6. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8344
www.icst.com
REV. B FEBRUARY 2, 2001
15
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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