8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8344I is a low voltage, low skew fanout
buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8344I has two selectable clock in-
puts. The CLK0, nCLK0 and CLK1, nCLK1 pairs
can accept most standard differential input levels. The
ICS8344I is designed to translate any differential signal lev-
els to LVCMOS levels. The low impedance LVCMOS outputs
are designed to drive 50
series or parallel terminated trans-
mission lines. The effective fanout can be increased to 48 by
utilizing the ability of the outputs to drive two series termi-
nated lines. Redundant clock applications can make use of
the dual clock input. The dual clock inputs also facilitate board
level testing. ICS8344I is characterized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
F
EATURES
24 LVCMOS outputs, 7
typical output impedance
2 selectable differential clock input pairs for redundant clock
applications
CLKx, nCLKx pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency up to 100MHz
Translates any single-ended input signal to LVCMOS with
resistor bias on nCLK input
Multiple output enable pins for disabling unused outputs in
reduced fanout applications
Output skew: 275ps (maximum)
Part-to-part skew: 600ps (maximum)
Bank skew: 150ps (maximum)
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
-40C to 85C ambient operating temperature
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
OE1
OE2
OE3
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
Q8
Q9
V
DDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q1
5
CLK0
nCLK0
OE1
OE2
OE3
Q0 - Q7
Q8 - Q15
Q16 - Q23
CLK_SEL
CLK1
nCLK1
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8344I
HiPerClockSTM
,&6
0
1
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
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7
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
T
ABLE
3C. C
LOCK
I
NPUTS
F
UNCTION
T
ABLE
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8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
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8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
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T
ABLE
5A. AC C
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8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
4E. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4F. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4D. P
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S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
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8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
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T
ABLE
4H. LVCMOS DC C
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DD
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DD
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= 2.5V5%, T
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= -40C
TO
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4G. P
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= V
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.
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
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T
ABLE
5C. AC C
HARACTERISTICS
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V
DD
= V
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8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
1A - 3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD
= +1.65V
V
DDO
= +1.65V
V
DD
GND = -1.65V
V
DDO
F
IGURE
1B - 2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DDO
= +1.25V
V
DDO
GND = -1.25V
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
3 - O
UTPUT
S
KEW
Qx
Qy
tsk(o)
SCOPE
Qx
LVCMOS
V
DD
= +2.05V
V
DDO
= +1.25V
V
DD
GND = -1.25V
V
DDO
F
IGURE
1C - 3.3V/2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
F
IGURE
2 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
CLK0, CLK1
nCLK0, nCLK1
GND
V
DD
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
7 - odc & t
P
ERIOD
CLK0, CLK1,
Q0 - Q23
nCLK0, nCLK1
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
F
IGURE
6 - P
ROPAGATION
D
ELAY
CLK0, CLK1
nCLK0, nCLK1
Q0 - Q23
tp
LH
tp
HL
V
DDOx
/2
F
IGURE
5 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
30%
70%
30%
70%
trise
tfall
V
S W I N G
F
IGURE
4 - P
ART
-
TO
-P
ART
S
KEW
Qx
Qy
PART 1
PART 2
tsk(pp)
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
F
IGURE
8 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
14
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8344I is: 1,449
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
15
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
C
C
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
8
4
A
0
6
.
1
1
A
5
0
.
0
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
7
1
.
0
2
2
.
0
7
2
.
0
c
9
0
.
0
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
0
5
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
0
5
.
5
e
C
I
S
A
B
5
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
7
c
c
c
8
0
.
0
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8344BYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 9, 2001
16
Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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