Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 3.3V/2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- 2.5V AC Characteristics
- 2.5V/1.8V AC Characteristics
- Parameter Measurement Information
- Parameter Measurement Information, continued
- Application Information
- VCXO Crystal Slection
- VCXO Oscillator Circuit Diagram
- Example Crystal Parameters Table
- Varactor Parameters Table
- Formulas
- Example Calculations
- Recommendations for Unused Input and Output Pins
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
81006AKI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
1
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
VCXO
0: 1
1: 2
SYNC
SYNC
LP Filter
G
ENERAL
D
ESCRIPTION
The ICS81006I is a high performance, low
j i t t e r / l o w p h a s e n o i s e V C X O a n d i s a
member of the HiPerClockSTM family of high
performance clock solutions from ICS. The
I C S 8 1 0 0 6 I w o r k s i n c o n j u n c t i o n w i t h a
pullable crystal to generate an output clock over the
range of 12MHz - 40MHz and has 6 LVCMOS outputs,
effectively integrating a fanout buffer function.
The frequency of the VCXO is adjusted by the VC control
voltage input. The output range is 100ppm around the
nominal crystal frequency. The VC control voltage range
is 0 - V
DD
. The device is packaged in a small 4mm x 4mm
V F Q F N p a c k a g e a n d i s i d e a l f o r u s e o n s p a c e
constrained boards typically encountered in ADSL/
VDSL applications.
F
EATURES
Six LVCMOS/LVTTL outputs, 20 nominal
output impedance
Output Q5 can be selected for 1 or 2 frequency relative
to the crystal frequency
Output frequency range: 12MHz to 40MHz
Crystal pull range: 90ppm (typical)
Synchronous output enable places outputs in High-Z state
On-chip filter on VIN to suppress noise modulation of VCXO
V
DD
/V
DDO
combinations
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
4mm x 4mm 20 Lead VFQFN package is ideal for space
constrained designs
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
OE0
VC
XTAL_IN
XTAL_OUT
DIV_SEL_Q5
OE1
Q0
Q1
Q2
Q3
Q4
Q5
(Pullup)
(Pulldown)
XTAL_IN
XTAL_OUT
V
DD
VC
DIV_SEL_Q5
GND
Q2
V
DDO
Q3
GND
OE1
GND
Q5
V
DDO
Q4
OE0
GND
Q0
V
DDO
Q1
1
2
3
4
5
20 19 18 17 16
ICS81006I
20-Lead VFQFN
4mm x 4mm x 0.95 package body
K Package
Top View
6 7 8 9 10
15
14
13
12
11
(Pullup)
81006AKI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
2
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
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81006AKI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
3
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
38.5C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 3.3V5% = 2.5V5%
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V5%, V
DDO
= 2.5V5%
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40C
TO
85C
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81006AKI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
4
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4C. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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81006AKI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
5
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
4D. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4E. AC C
HARACTERISTICS
,
V
DD
= 2.5V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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81006AKI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 19, 2006
6
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.4V0.065V
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
SCOPE
Qx
LVCMOS
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDO
-1.25V5%
V
DD
1.25V5%
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5 C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
SCOPE
Qx
LVCMOS
1.6V0.025V
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
V
DD
,
V
DDO
GND
GND
GND
GND
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
V
DD
,
V
DDO
GND
81006AKI
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REV. A JANUARY 19, 2006
7
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
S
KEW
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
t
PW
Q0:Q5
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
sk(o)
V
DDO
2
V
DDO
2
Qy
Qx
81006AKI
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REV. A JANUARY 19, 2006
8
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
Oscillator
A
PPLICATION
I
NFORMATION
F
IGURE
1: VCXO O
SCILLATOR
C
IRCUIT
V
C
C
V
C
S 1
C
L1
C
S 2
C
L2
C
V
XTAL
VCXO (Internal)
Optional
Control Voltage
T
ABLE
5. E
XAMPLE
C
RYSTAL
P
ARAMETERS
l
o
b
m
y
S
r
e
t
e
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a
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a
P
s
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o
i
t
i
d
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o
C
t
s
e
T
m
u
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n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
N
y
c
n
e
u
q
e
r
F
l
a
n
i
m
o
N
4
4
.
9
1
z
H
M
f
T
e
c
n
a
r
e
l
o
T
y
c
n
e
u
q
e
r
F
0
2
m
p
p
f
S
y
t
il
i
b
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S
y
c
n
e
u
q
e
r
F
0
2
m
p
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e
g
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a
R
e
r
u
t
a
r
e
p
m
e
T
g
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i
t
a
r
e
p
O
0
0
7
C
C
L
e
c
n
a
t
i
c
a
p
a
C
d
a
o
L
2
1
F
p
C
O
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
4
F
p
C
,
0
C
1
o
i
t
a
R
y
t
il
i
b
a
ll
u
P
0
2
2
0
4
2
R
S
E
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
2
l
e
v
e
L
e
v
i
r
D
1
W
m
C
5
2
@
g
n
i
g
A
r
a
e
y
r
e
p
3
m
p
p
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t
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a
d
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u
F
VCXO C
RYSTAL
S
ELECTION
Choosing a crystal with the correct characteristics is one of
the most critical steps in using a Voltage Controlled Crystal
Oscillator (VCXO). The crystal parameters affect the tuning
V
C
Control voltage used to tune frequency
C
V
Varactor capacitance, varies due to the change in
control voltage
range and accuracy of a VCXO. Below are the key variables
and an example of using the crystal parameters to calculate
the tuning range of the VCXO.
C
L1,
C
L2
Load tuning capacitance used for fine tuning or
centering nominal frequency
C
S1,
C
S2
Stray Capacitance caused by pads, vias, and other
board parasitics
81006AKI
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REV. A JANUARY 19, 2006
9
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
W
O
L
_
V
e
c
n
a
t
i
c
a
p
a
C
r
o
t
c
a
r
a
V
w
o
L
V
C
V
0
=
4
.
5
1
F
p
C
H
G
I
H
_
V
e
c
n
a
t
i
c
a
p
a
C
r
o
t
c
a
r
a
V
h
g
i
H
V
C
V
3
.
3
=
6
.
9
2
F
p
T
ABLE
6. V
ARACTOR
P
ARAMETERS
F
ORMULAS
(
) (
)
(
) (
)
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
C
C
C
C
C
C
C
C
C
C
C
C
C
_
2
2
_
1
1
_
2
2
_
1
1
+
+
+
+
+
+
+
+
+
=
(
) (
)
(
) (
)
High
V
S
L
High
V
S
L
High
V
S
L
High
V
S
L
High
C
C
C
C
C
C
C
C
C
C
C
C
C
_
2
2
_
1
1
_
2
2
_
1
1
+
+
+
+
+
+
+
+
+
=
6
0
1
0
0
1
0
10
1
2
1
1
2
1
)
(
+
-
+
=
C
C
C
C
C
C
C
C
TPR
Range
Pull
Total
High
Low
C
Low
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C
Low
determines the high frequency component on the TPR.
C
High
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C
High
determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range (Frequency Tolerance + Frequency Stability + Aging)
E
XAMPLE
C
ALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were some
assumptions made. First, the stray capacitance (C
S1
, C
S2
), which
is all the excess capacitance due to board parasitic, is 4pF.
Second, the expected lifetime of the project is 5 years; hence
the inaccuracy due to aging is 15ppm. Third, though many
boards will not require load tuning capacitors (C
L1
, C
L2
), it is
recommended for long-term consistent performance of the
system that two tuning capacitor pads be placed into every
design. Typical values for the load tuning capacitors will range
from 0 to 4pF.
(
) (
)
(
) (
)
pf
pf
pf
pf
pf
pf
pf
pf
pf
C
Low
7
.
9
4
.
15
4
0
4
.
15
4
0
4
.
15
4
0
4
.
15
4
0
=
+
+
+
+
+
+
+
+
+
=
(
) (
)
(
) (
)
pf
pf
pf
pf
pf
pf
pf
pf
pf
C
High
8
.
16
6
.
29
4
0
6
.
29
4
0
6
.
29
4
0
6
.
29
4
0
=
+
+
+
+
+
+
+
+
+
=
ppm
pF
pF
pF
pF
TPR
5
.
226
10
4
8
.
16
1
220
2
1
4
7
.
9
1
220
2
1
6
=
+
-
+
=
TPR = 113.25ppm
APR = 113.25ppm (20ppm + 20ppm + 15ppm) = 58.25ppm
The example above will ensure a total pull range of
113.25 ppm with an APR of 58.25ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
81006AKI
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REV. A JANUARY 19, 2006
10
Integrated
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Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
S
CHEMATIC
E
XAMPLE
Figure 2
shows an example of ICS81006I application sche-
matic. The decoupling capacitors should be located as close
as possible to the power pin. For the LVCMOS 20
output
drivers, series termination example is shown in the sche-
matic. Additional termination approaches are shown in the
LVCMOS Termination Application Note.
F
IGURE
2. ICS81006I S
CHEMATIC
E
XAMPLE
I
NPUTS
:
C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used. The VC pin can not be
floated.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
C2
SPARE
R5
1K
VC = 0V to VDD
VDD
C1
SPARE
U1
81006
2
3
4
5
6
7
8
9
11
12
13
14
17
18
19
20
10
16
15
1
XTAL_OUT
VDD
VC
DIV_SEL_Q5
OE
1
GN
D
Q5
VD
D
O
GND
Q3
VDDO
Q2
VD
D
O
Q0
GN
D
OE
0
Q4
Q
1
GND
XTAL_IN
Zo = 50
(U1-13)
C3
0.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
C6
0.1uF
C5
0.1uF
C7
10uf
Pull-up
example
(U1-9)
R4
1K
Quartz crystal should be
placed as close to the
device as possible.
VDDO
Pull-down
example
VDD
R3
1K
VDDO
R1
30
VDD
R2
30
VC
C4
0.1uF
XTAL
(U1-17)
Zo = 50
VDD
(U1-3)
81006I
81006AKI
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REV. A JANUARY 19, 2006
11
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS81006I is: 983
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
VFQFN
JA
by Velocity (Meters Per Second)
0
1
2.5
Single-Layer PCB, JEDEC Standard Test Boards
141.7C/W
126.0C/W
116.9C/W
Multi-Layer PCB, JEDEC Standard Test Boards
38.5C/W
35.0C/W
33.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
81006AKI
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REV. A JANUARY 19, 2006
12
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
P
ACKAGE
O
UTLINE
- K S
UFFIX
FOR
20 L
EAD
VFQFN
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-220
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
M
U
M
I
N
I
M
M
U
M
I
X
A
M
N
0
2
A
0
8
.
0
0
.
1
1
A
0
5
0
.
0
3
A
e
c
n
e
r
e
f
e
R
5
2
.
0
b
8
1
.
0
0
3
.
0
e
C
I
S
A
B
0
5
.
0
N
D
5
N
E
5
D
0
.
4
2
D
5
7
.
0
0
8
.
2
E
0
.
4
2
E
5
7
.
0
0
8
.
2
L
5
3
.
0
5
7
.
0
To p View
Ind ex Area
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A 3
A1
S eating Plan e
E 2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Ba se
N
OR
81006AKI
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REV. A JANUARY 19, 2006
13
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical
medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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