ICS671-05
MDS 671-05 F
1
Revision 030403
I n t e g r a t e d Ci r c u i t S y s t e m s
l
5 2 5 Ra c e St r e e t , S a n J o s e , CA 9 5 1 2 6
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t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
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w w w. i c s t . c o m
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Description
The ICS671-05 is a low phase noise, high speed PLL
based, 8 output, low skew zero delay buffer. Based on
ICS' proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew outputs
at speeds up to 133 MHz at 3.3V. The outputs can be
generated from the PLL (for zero delay), or directly
from the input (for testing), and can be set to tri-state
mode or to stop at a low level. For normal operation as
a zero delay buffer, any output clock is tied to the FBIN
pin.
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
Features
Clock outputs from 10 to 133 MHz
Zero input-output delay
Eight low skew (<200 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 25mA output drive capability
at TTL levels
5V tolerant FBIN and CLKIN pins
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3V
Industrial temperature range available
Packaged in 16 pin SOIC and TSSOP packages
Block Diagram
CLKA4
CLKB1
CLKA3
CLKB2
CLKB3
CLKA2
CLKA1
CLKB4
CLKIN
Control
Logic
1
0
S2, S1
2
Clock
Synthesis
PLL
FBIN
Feedback is shown from CLKB4 for
illustration, but may come from any output.
VDD
2
GND
2
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
MDS 671-05 F
2
Revision 030403
I n t e g r a t e d C i r c u i t S y s t e m s
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5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6
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t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
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ICS671-05
Pin Assignment
Output Clock Mode Select Table
Note 1. Outputs are in high impedence state
Note 2. Buffer mode only; not zero delay between input and output
Pin Descriptions
1 2
1
1 1
2
1 0
C L K IN
F B IN
3
9
C L K A 1
4
C L K A 2
C L K A 4
5
V D D
6
C L K A 3
7
G N D
8
C L K B 1
V D D
G N D
C L K B 4
C L K B 2
C L K B 3
S 2
S 1
1 6
1 5
1 4
1 3
1 6 p in n a rro w (1 5 0 m il) S O IC
a n d 1 6 p in (1 7 3 m il ) T S S O P
S2
S1
CLKA1:A4
CLKB1:B4
A & B Source
PLL Status
0
0
Tri-state (note 1)
Tri-state (note 1)
PLL
OFF
0
1
Running
Tri-state (note 1)
PLL
ON
1
0
Running
Running
CLKIN (note 2)
OFF
1
1
Running
Running
PLL
ON
Pin
Number
Pin
Name
Pin Type
Pin Description
1
CLKIN
Input
Clock input (5 V tolerant).
2 - 3
CLKA1:A4
Output
Clock outputs A1:A4. See table above.
4
VDD
Power
Power supply. Connect to 3.3 V.
5
GND
Power
Connect to ground.
6 - 7
CLKB1:B4
Output
Clock outputs B1:B4. See table above.
8
S2
Input
Select input 2. See table above. Internal pull-up.
9
S1
Input
Select input 1. See table above. Internal pull-up.
10 - 11
CLKB1:B4
Output
Clock outputs B1:B4. See table above.
12
GND
Power
Connect to ground.
13
VDD
Power
Power supply. Connect to 3.3 V.
14 - 15
CLKA1:A4
Output
Clock outputs A1:A4. See table above.
16
FBIN
Input
Feedback input. Connect to any output under normal operation (5V tolerant).
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
MDS 671-05 F
3
Revision 030403
I n t e g r a t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
l
w w w. i c s t . c o m
ICS671-05
External Components
The ICS671-05 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01mF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on
pins 13 and 12, as close to the device as possible. A series termination resistor of 33
may be used to
each clock output pin to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS671-05. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=3.3V 10%,
Ambient temperature -40 to +85
C, unless stated otherwise
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
CLKIN and FBIN inputs
-0.5V to 5.5V
Electrostatic Discharge
2000 V
Ambient Operating Temperature
0 to +70
C
Industrial Temperature
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
150
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
3.6
V
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Input Low Current
I
IL
VIN = 0V
50
A
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
MDS 671-05 F
4
Revision 030403
I n t e g r a t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
l
w w w. i c s t . c o m
ICS671-05
AC Electrical Characteristics
VDD = 3.3V 10%,
Ambient Temperature -40 to +85
C, unless stated otherwise
Note 1: With CLKIN = 100MHz, FBIN to CLKA4, all outputs at 100 MHz
Note 2: When there is no clock signal present at CLKIN, the ICS671-05 will enter power down mode. The
PLL is stopped and the outputs are tri-state.
Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN
Input High Current
I
IH
VIN = VDD
100
A
Output High Voltage
V
OH
I
OH
= -12 mA
2.4
V
Ouput Low Voltage
V
OL
I
OL
= 12 mA
0.4
V
Output High Voltage,
CMOS level
V
OH
I
OH
= -4 mA
VDD-0.4
V
Operating Supply Current
IDD
No Load, S2 = 1, S1 = 1,
Note 1
70
mA
Power Down Supply
Current
IDDPD
CLKIN = 0, S2 = 0, S1 = 1
12
A
CLKIN = 0, Note 2
12
A
Short Circuit Current
I
OS
Each output
50
mA
Input Capacitance
C
IN
S2, S1, FBIN
5
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Clock Frequency
f
IN
See table on page 2
10
133
MHz
Output Clock Frequency
See table on page 2
10
133
MHz
Output Rise Time
t
OR
0.8 to 2.0V, CL=30pF
1.5
ns
Output Fall Time
t
OF
2.0 to 0.8V, CL=30pF
1.25
ns
Output Clock Duty Cycle
t
DC
measured at VDD/2
45
50
55
%
Device to Device Skew
rising edges at VDD/2
700
ps
Output to Output Skew
rising edges at VDD/2
200
ps
Input to Output Skew
rising edges at VDD/2, FBIN to
CLKA4, S1 = 1, S0 = 1, Note 1
250
ps
Maximum Absolute JItter
CL=15pF, measured at 66.67M
130
ps
Cycle to Cycle Jitter
CL=30pF, measured at 66.67M
200
ps
CL=15pF, measured at 66.67M
200
ps
CL=15pF, measured at 133.33M
100
ps
PLL Lock Time
Note 3
1.0
ms
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
MDS 671-05 F
5
Revision 030403
I n t e g r a t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
l
w w w. i c s t . c o m
ICS671-05
Thermal Characteristics (16 pin SOIC)
Thermal Characteristics (16 pin TSSOP)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
120
C/W
JA
1 m/s air flow
115
C/W
JA
3 m/s air flow
105
C/W
Thermal Resistance Junction to Case
JC
58
C/W
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
MDS 671-05 F
6
Revision 030403
I n t e g r a t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
l
w w w. i c s t . c o m
ICS671-05
Package Outline and Package Dimensions
(16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
16
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004)
C
C
L
H
h x 45
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
1.35
1.75
.0532
.0688
A1
0.10
0.25
.0040
.0098
B
0.33
0.51
.013
.020
C
0.19
0.25
.0075
.0098
D
9.80
10.00
.3859
.3937
E
3.80
4.00
.1497
.1574
e
1.27 BASIC
0.050 BASIC
H
5.80
6.20
.2284
.2440
h
0.25
0.50
.010
.020
L
0.40
1.27
.016
.050
0
8
0
8
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
MDS 671-05 F
7
Revision 030403
I n t e g r a t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
l
w w w. i c s t . c o m
ICS671-05
Package Outline and Package Dimensions
(16 pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as
those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS671M-05I
ICS671M-05
Tubes
16 pin SOIC
-40 to +85
C
ICS671M-05IT
ICS671M-05
Tape and Reel
16 pin SOIC
-40 to +85
C
ICS671G-05I
ICS671G-05I
Tubes
16 pin TSSOP
-40 to +85
C
ICS671G-05IT
ICS671G-05I
Tape and Reel
16 pin TSSOP
-40 to +85
C
IN D E X
A R E A
1 2
16
D
E 1
E
S E A T IN G
P L A N E
A
1
A
A
2
e
- C -
b
aa a
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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