ICS554-01A
MDS 554-01A A
1
Revision 101904
I n t e gra t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
PECL I
N
, PECL O
UT
Description
The ICS554-01A is a low skew clock buffer with a
single complimentary PECL input to four PECL
outputs. Part of ICS' Clock Blocks
TM
family, this is our
lowest skew PECL clock buffer. The ICS554-01A is
footprint compatible with the ICS554-01, but requires
fewer passive components for termination thus
providing a cost-saving alternative. For parts which do
not require PECL inputs or outputs, see the ICS553 for
a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8
low skew buffer. For more than 8 outputs see the
MK74CBxxx Buffalo
TM
series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
Input frequency up to 200 MHz
Advanced CMOS process
Outputs are skew matched to within 50 ps
Packaged in 16-pin TSSOP
One PECL input to 4 PECL output clock drivers
Operating Voltages of 3.3 V or 5 V
Industrial temperature range
Functional equivalent to ICS554-01
Simplified passive termination network compared to
ICS554-01
Block Diagram
IN
IN
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VDD
VSS
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
PECL I
N
, PECL O
UT
MDS 554-01A A
2
Revision 101904
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS554-01A
Pin Assignment
Pin Descriptions
12
1
11
2
10
3
9
NC
4
VDD
5
6
VDD
7
Q0
8
Q3
Q3
Q2
Q1
IN
GND
GND
16
15
14
13
IN
NC
16-pin 173 mil (0.65mm) TSSOP
Q0
Q1
Q2
Number
Name
Type
Pin Description
1
NC
--
No Connect.
2
VDD
Power
Connect to +3.3 V or 5 V. Must be same as pin 15.
3
Q0
Output
Clock Output Q0.
4
Q0
Output
Clock Output Q0.
5
Q1
Output
Clock Output Q1.
6
Q1
Output
Clock Output Q1.
7
GND
Power
Connect to Ground.
8
IN
Input
PECL Clock Input.
9
IN
Input
Complementary PECL Clock Input.
10
GND
Power
Connect to Ground
11
Q2
Output
Clock Output Q2.
12
Q2
Output
Clock Output Q2.
13
Q3
Output
Clock Output Q3.
14
Q3
Output
Clock Output Q3.
15
VDD
Power
Connect to +3.3 V or 5 V. Must be same as pin 2.
16
NC
--
No Connect.
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
PECL I
N
, PECL O
UT
MDS 554-01A A
3
Revision 101904
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS554-01A
External Components
The ICS554-01A requires a decoupling capacitor of 0.01
F to be connected between VDD on pin 2 and
GND on pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should
be placed as close to the device as possible.
To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do
not, the output skew will be degraded. For example, using a 30
series termination on one output (with
33
on the others) will cause at least 15ps of skew.
Termination for PECL or LVPECL Outputs
The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two
different layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs.
Therefore, termination resistors (DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50 ohm transmission lines. Matched impedance
techniques should be used to maximize operating frequency and minimize signal distortion. There are a
few simple termination schemes. The figures below show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist, but it is recommended that board designers
simulate to guarantee compatibility across all printed circuit and clock component process variations.
PECL or LVPECL Output Termination
LVPECL Output Termination
Z
0
= 50 ohms
F
OUT
F
IN
Z
0
= 50 ohms
50 ohms
50 ohms
C1
RTT
RTT =
Z
0
(V
OH
+
V
OL
/
V
CC
-2) -2
1
C1 = 0.1F to 0.01F
Z
0
= 50 ohms
F
OUT
F
IN
Z
0
= 50 ohms
Z
0
3.3 V
5
2
3 2
5
2
Z
0
Z
0
3 2
Z
0
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
PECL I
N
, PECL O
UT
MDS 554-01A A
4
Revision 101904
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS554-01A
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS554-01A. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.15
+5.25
V
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
PECL I
N
, PECL O
UT
MDS 554-01A A
5
Revision 101904
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS554-01A
DC Electrical Characteristics
VDD=3.3 V 5%
Ambient temperature -40 to +85
C
Note 1: V
OH
and V
OL
can be set by the external resistor values on the PECL outputs.
note 2: IDD includes the current through the external resistors which can be modified.
AC Electrical Characteristics
VDD = 3.3 V 5
,
Ambient Temperature -40 to +85
C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
5.25
V
Peak to Peak Input Voltage
IN
0.3
1.0
V
Input Common Mode Range
IN
VDD=3.3 V
VDD-2
VDD-0.6
Input Common Mode Range
IN
VDD=5 V
VDD-3.7
VDD-0.6
Output High Voltage
V
OH
Note 1
VDD-1.2
V
Output Low Voltage
V
OL
Note 1
VDD - 2.0
V
Operating Supply Current
IDD
No Load, 135 MHz
80
mA
Short Circuit Current, 3.3 V
I
OS
50
mA
Short Circuit Current, 5 V
I
OS
60
mA
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Propagation Delay
VDD = 3.3 V
2
ns
VDD = 5 V
2
ns
Output to Output Skew
Crosspoint of pair
0
50
ps
Duty Cycle
Crosspoint of pair
45
50
55
%
L
OW
S
KEW
1
TO
4 C
LOCK
B
UFFER
PECL I
N
, PECL O
UT
MDS 554-01A A
6
Revision 101904
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS554-01A
Package Outline and Package Dimensions
(16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS554GI-01A
ICS (top line)
Tubes
16-pin TSSOP
-40 to +85
C
ICS554GI-01AT
554GI01A (2nd line)
Tape and Reel
16-pin TSSOP
-40 to +85
C
IN D E X
A R E A
1 2
16
D
E 1
E
S E A T IN G
P LA N E
A
1
A
A
2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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