ICS548-06
MDS 548-06 B
1
Revision 091702
I n t e g r a t e d C i r cu i t S y st e m s
q
5 2 5 Ra ce S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. i c s t . c o m
LOCO PLL C
LOCK
M
ULTIPLIER
Description
The ICS548-06 LOCO is a cost effective way to
generate high quality, high frequency clock outputs and
a reference clock from a lower frequency crystal or
clock input. The name LOCO stands for LOw Cost
Oscillator, as it is designed to replace crystal oscillators
in most electronic systems. Using Phase-Locked-Loop
(PLL) techniques, the device uses a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 200MHz.
Stored in the chip's ROM is the ability to generate nine
different popular multiplication factors, allowing one
chip to output many common frequencies.
Features
Zero ppm multiplication error
Packaged in 16 pin TSSOP
Low power CMOS technology
Easy to cascade with other 5xx series
Input crystal frequency of 5-27 MHz
Input clock frequency of 2-50 MHz
Output clock frequencies up to 200 MHz
Duty Cycle of 45/55 up to 200 MHz
Operating voltage of 3.3 or 5V
Advanced, low power CMOS process
Block Diagram
CLK1
Clock
Buffer/
Crystal
Oscillator
X1/ICLK
X2
S1, S0
Crystal or
clock input
PLL
Clock
Synthesis
and
Control
Circuitry
REF
VDD
GND
2
2
Optional crystal capacitors
2
CLK2
/2
REFSEL
PDCLK2
OE
LOCO PLL C
LOCK
M
ULTIPLIER
MDS 548-06 B
2
Revision 091702
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
ICS548-06
Pin Assignment
Reference Clock Output Table
Clock Output Table
Pin Descriptions
12
1
11
2
10
3
9
X1/ICLK
4
VDD
5
VDD
6
DC
7
REFSEL
8
GND
PDCLK2
OE
DC
GND
S0
CLK1
REF
CLK2
16
15
14
13
S1
X2
16-Pin 173 Mil (0.65mm) TSSOP
REFSEL
REF
0
ON
1
OFF
S1
S0
CLK1
CLK2
0
0
4X input
2X input
0
M
5.333X input
2.667X input
0
1
5X input
2.5X input
M
0
2.5X input
1.25X input
M
M
2X input
1X input
M
1
3.333X input
1.667X input
1
0
6X input
3X input
1
M
3X input
1.5X input
1
1
8X input
4X input
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
Input
Crystal connection or clock input.
2
VDD
Power
Connect to +3.3V or +5.0V. Must be the same as pin 3.
3
VDD
Power
Connect to +3.3V or +5.0V. Must be the same as pin 2.
4
REFSEL
Input
Turns off reference clock when high. Internal pull-up.
5
GND
Power
Connect to ground.
6
GND
Power
Connect to ground.
7
REF
Output
Reference clock output.
8
S1
Input
Multiplier select pin 1. Connect to GND, VDD or float.
9
CLK1
Output
Clock1 output per table above.
10
CLK2
Output
Clock2 output per table above.
11
S0
Input
Multiplier select pin 0. Connect to GND, VDD or float.
12
DC
-
Do not connect anything to this pin.
13
OE
Input
Output enable.
14
PDCLK2
Input
Turns off Clock2 when high. Internal pull-up.
15
DC
-
Do not connect anything to this pin.
16
X2
Input
Crystal connection. Leave unconnected for clock input.
LOCO PLL C
LOCK
M
ULTIPLIER
MDS 548-06 B
3
Revision 091702
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
ICS548-06
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01
F should be connected between VDD on pin 2 and GND on pin 5, and between VDD on pin 3 and
GND on pin 6, as close to the device as possible. A 33
series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS548-06. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
175
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.0
+5.5
V
LOCO PLL C
LOCK
M
ULTIPLIER
MDS 548-06 B
4
Revision 091702
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
ICS548-06
DC Electrical Characteristics
VDD=3.3 V 10%
, Ambient temperature 0 to +70
C, unless stated otherwise
Note: 1. Using a 20MHz crystal input, outputs of 100MHz and 50MHz.
AC Electrical Characteristics
VDD = 3.3V 10%
, Ambient Temperature 0 to +70
C, unless stated otherwise
Note:1. The phase relationship between input and output clocks can change at power up. For a fixed
phase relationship, see the ICS570 or the ICS527.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
Input High Voltage, ICLK only
V
IH
Pin 1
(VDD/2)+1
VDD/2
5.5
V
Input Low Voltage, ICLK only
V
IL
Pin 1
VDD/2
(VDD/2)-1
V
Input High Voltage, S0, S1
V
IH
VDD-0.5
V
Input Low Voltage, S0, S1
V
IL
0.5
V
Output High Voltage
V
OH
I
OH
= -8 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -25 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 20 mA
0.4
V
Short Circuit Current
I
OS
Each output
70
mA
Operating Supply Current
I
DD
Note 1
11
mA
Input Capacitacnce, S1, S0
C
IN
5
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency, crystal input
5
27
MHz
Input Frequency, clock input
2
50
MHz
Output Frequency, VDD=5V
14
200
MHz
Output Frequency, VDD=3.3V
14
160
MHz
Output Rise Time
t
OR
0.8 to 2.0 V, C
L
=15 pF
600
ps
Output Fall Time
t
OF
2.0 to 0.8 V, C
L
=15 pF
600
ps
Output clock duty cycle
at VDD/2
45
49 to 51
55
%
Absolute Clock Period Jitter
Deviation from mean
150
ps
One Sigma Clock Period Jitter
75
ps
Skew
CLK1 to CLK2
-250
250
ps
LOCO PLL C
LOCK
M
ULTIPLIER
MDS 548-06 B
5
Revision 091702
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
ICS548-06
Package Outline and Package Dimensions
(16 pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking(both)
Shipping
packaging
Package
Temperature
ICS548G-06
ICS (top line)
Tubes
16 pin TSSOP
0 to +70
C
ICS548G-06T
548G-06 (2nd line)
Tape and Reel
16 pin TSSOP
0 to +70
C
INDEX
AREA
1 2
16
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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