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Электронный компонент: ICS426G

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ICS426
MDS 426 B
1
Revision 091102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
Serial ATA/Fibre Channel Clock Synthesizer
Description
The ICS426 was developed for serial ATA (SATA) and
fiber channel. It generates a high quality, high
frequency clock output from a low cost frequency
crystal or clock input.
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal or clock input.
Features
Packaged in 16 pin TSSOP
Input crystal or clock frequency of 25 MHz (typical)
Supports serial ATA Generation 1
Supports Fiber Channel
Duty cycle of 45/55
Operating voltage of 3.3V
Advanced, low power, CMOS process
Block Diagram
X1
X2
PLL /Clock
Synthesis
Circuitry
Crystal
O scillator
25 MHz
Crystal or
Clock Input
Capacitors may be
required with a crystal input.
CLK
G ND
6
S0:S1
O E
VDD
4
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
2
Revision 091102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
ICS426
Pin Assignment
Clock Output Select Table (MHz)
Pin Descriptions
12
1
11
2
10
3
9
X1/ICLK
4
VDD
5
VDD
6
GND
7
GND
8
GND
GND
OE
GND
S1
S0
GND
VDD
VDD
16
15
14
13
CLK
X2
16 pin 173 mil (0.65 mm) TSSOP
S1
S0
Input
CLK Output
0
0
25
75
0
1
25
150
1
0
25
106.25
1
1
25
156.25
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
XI
Crystal connection. Connect to a 25 MHz fundamental mode
crystal or clock input.
2
VDD
Power
Connect to +3.3 V.
3
VDD
Power
Connect to +3.3 V.
4
GND
Power
Connect to ground.
5
GND
Power
Connect to ground.
6
S1
Input
Select pin 1 determines CLK output based on table above. Internal
pull-up.
7
VDD
Power
Connect to +3.3 V.
8
CLK
Output
Clock output. Tri-state output when OE is low.
9
GND
Power
Connect to ground.
10
VDD
Power
Connect to +3.3V.
11
S0
Input
Select pin 0 determines CLK output based on table above. Internal
pull-up.
12
GND
Power
Connect to ground.
13
OE
Input
Output Enable. All outputs are tri-stated when low. Internal pull-up.
14
GND
Power
Connect to ground.
15
GND
Power
Connect to ground.
16
X2
XO
Crystal connection. Connect to a 25 MHz fundamental mode
crystal or float for clock input.
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
3
Revision 091102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
ICS426
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS426 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-18pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 20 pF
load capacitance, each crystal capacitor would be 4 pF
[(20-18) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS426. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
4
Revision 091102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
ICS426
Phase Noise Graph
25 MHz crystal input, 106.25 MHz CLK output.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS426. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
175
C
Soldering Temperature
260
C
Phase Noise 106.25 M Hz
-140
-120
-100
-80
-60
-40
-20
0
1E+3
10E+3
100E+3
1E+6
10E+6
offset frequency
L(f) dBc
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
5
Revision 091102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
ICS426
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70
C
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70
C
Note 1: Measured with 15 pF load.
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.13
+3.3
+3.46
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.13
3.3
3.47
V
Supply Current
IDD
No load
22
mA
Input High Voltage
V
IH
OE, S0, S1
2
V
Input Low Voltage
V
IL
OE, S0, S1
0.8
V
Output High Voltage
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 12mA
0.4
V
Short Circuit Current
I
OS
CLK output
50
mA
On Chip Pull-up Resistor
R
PU
OE, S0, S1
150
k
Input Capacitance
C
IN
OE, S0, S1
5
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
Crystal or clock input
25
MHz
Output Clock Duty Cycle
Measured at VDD/2, Note 1
45
50
55
%
Output Rise Time
t
OR
0.8 to 2.0V, Note 1
1
ns
Output Fall Time
t
OF
2.0 to 0.8V, Note 1
1
ns
Short Term Jitter
peak to peak, Note 1
70
ps
Long Term Jitter
Measured over 1000 cycles;
peak to peak, Note 1
170
ps
Phase Noise
106.25M CLK, relative to carrier,
100 Hz offset
-90
dBc/Hz
106.25M CLK, relative to carrier,
1kHz offset
-115
dBc/Hz
106.25M CLK, relative to carrier,
10 kHz offset
-121
dBc/Hz
106.25M CLK, relative to carrier,
100 kHz offset
-116
dBc/Hz
Serial ATA/Fibre Channel Clock Synthesizer
MDS 426 B
6
Revision 091102
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
ICS426
Package Outline and Package Dimensions
(16 pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
(both)
Shipping
packaging
Package
Temperature
ICS426G
ICS426G
Tubes
16 pin TSSOP
0 to +70
C
ICS426GT
ICS426G
Tape and Reel
16 pin TSSOP
0 to +70
C
IN D E X
A R E A
1 2
16
D
E 1
E
S E A T IN G
P L A N E
A
1
A
A
2
e
- C -
b
aa a
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004