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Электронный компонент: IC66LV10016AL-70B

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Integrated Circuit Solution Inc.
1
PSR002-0A 02/05/2004
IC66LV10016AL
Document Title
16M-BIT (1M-WORD BY 16-BIT) Low Power Pseudo SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
February 05,2004
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
2
Integrated Circuit Solution Inc.
PSR002-0A 02/05/2004
IC66LV10016AL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Organization : 1M x 16
Power Supply Voltage : 2.7~3.3V
Three state output and TTL Compatible
Package Type : 48-FBGA-6.00x8.00 mm
2
Address Acess Time : 70ns
16M-BIT (1M-WORD BY 16-BIT) Low-Power Pseudo SRAM
DESCRIPTION
The IC66LV10016AL is a family of low voltage, low power
16Mbit static RAM organized as 1M-words by 16-bit,
designed with Pseudo SRAM technology, fabricated with
CMOS process technology.
The IC66LV10016AL is designed specifically for low-power
applications such as mobile cellular phones, personal digital
assistants and other battery-operated products.
The operation modes are determined by a combination of the
device control inputs CE , ZZ, LB , UB , WE and OE . Each
mode is summarized in the function table.
A write operation is executed whenever the low level WE
overlaps with the low level LB and/or UB and the low level CE
and the high level ZZ. The address (A0~A19) must be set up
before the write cycle and must be stable during entire cycle.
A read operation is executed by setting WE at a high level and
OE at a low level while LB and/or UB and CE are in an active
state, ZZ is in a inactive state.
When setting LB at the high level and other controls are in an
active stage, upper-byte is selected for read and write
operations, and lower-byte is not selected. When setting UB
at a high level and other pins are in an active stage, lower-byte
is selected and upper-byte is not.
When setting LB and UB at a high level or CE and ZZ at a high
level or ZZ at a low level, the chip is in a non-select mode. In
this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips.
When OE is at a high level, the output stage is in a high-
impedance state.
PART NAME TABLE & KEY SPEC SUMMARY
Deep powe
Product Family
Operating Operating Voltage Speed
down
Standby
Operating PKG Type
Temperature
(VCC/VCCQ)
(I
ZZ
,Max) (I
SB
2,Max) (Icc2,Max)
IC66LV10016AL-70B Extended
2.7-3.3V
70ns
25A
70A
20mA
48-TFBGA
(-25-85C)
Integrated Circuit Solution Inc.
3
PSR002-0A 02/05/2004
IC66LV10016AL
FUNCTIONAL BLOCK DIAGRAM
CE
OE
WE
UB
LB
ZZ
Control
Logic
Data
Cont
Data
Cont
Data
Cont
Row
select
Clk gen.
Precharge circuit
Memory array
VCC
VSS
Row
Addresses
I/O1~I/O8
I/O9~I/O16
I/O Circuit
Column select
Column Addresses
4
Integrated Circuit Solution Inc.
PSR002-0A 02/05/2004
IC66LV10016AL
1 2 3
4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A3
A1
A2
ZZ
I/O9
UB
A4
CE
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
VSS
I/O12
A17
A7
I/O4
VCC
VCC I/O13
NC
A16
I/O5
VSS
I/O15
I/O14
A14
A15 I/O6
I/O7
I/O16
A19
A12
A13
WE
I/O8
A18
A8
A9
A10
A11
NC
(TOP VIEW)
48-TFBGA
Pin
Function
A0~A19
Address input
I/O1 ~ I/O16
Data input / output
ZZ
Low power modes
CE
Chip select input
WE
Write enable input
OE
Output enable input
UB
Upper Byte (I/O9 ~ 16)
LB
Lower Byte (I/O1 ~ 8)
VCC
Power supply
VSS
Ground supply
NC
No connection
PIN CONFIGURATIONS
FUNCTION TABLE
CE
ZZ
OE
WE
LB
UB
I/O1-8
I/O9-16
Mode
Power
H
H
X
(1)
X
(1)
X
(1)
X
(1)
High-Z
High-Z
Deselected
Standby
X
(1)
L
X
(1)
X
(1)
X
(1)
X
(1)
High-Z
High-Z
Deselected
Deep Power Down Mode
L
H
H
H
X
(1)
X
(1)
High-Z
High-Z
Output disabled
Active
L
H
X
(1)
H
H
H
High-Z
High-Z
Output disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower byte read
Active
L
H
L
H
H
L
High-Z
Dout
Upper byte read
Active
L
H
L
H
L
L
Dout
Dout
Word read
Active
L
H
H
L
L
H
Din
High-Z
Lower byte write
Active
L
H
H
L
H
L
High-Z
Din
Upper byte write
Active
L
H
H
L
L
L
Din
Din
Word write
Active
Notes:
1. X means don't-care.(Must be low or hight state)
Integrated Circuit Solution Inc.
5
PSR002-0A 02/05/2004
IC66LV10016AL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Unit
V
IN
,V
OUT
Voltage on any pin relative to Vss
-0.2 to Vcc+0.3
V
Vcc
Voltage on Vcc supply relative to Vss
-0.2 to 3.6
V
PD
Power Dissipation
1.0
W
T
STG
Storage Temperature
-65 to 150
C
Toper
Operating Temperature
-25 to 85
C
Note:
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(1)
Symbol
Parameter
Conditions
Min
Max
Units
V
CC
Supply Voltage
2.7
3.3
V
V
IH
Input High Voltage
Vcc-0.3
Vcc+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(3)
0.3
V
I
LI
Input Leakage current
V
IN
=Vss to Vcc
-1
1
A
I
LO
Output Leakage current V
OUT
=Vss to Vcc
-1
1
A
Output Disable
V
OL
Output low Voltage
I
OL
=0.5mA
0.3
V
V
OH
Output high Voltage
I
OH
=-0.5mA
Vcc-0.3
V
Notes:
1. Toper=-25 to 85C, otherwise specified.
2. Overshoot : Vcc+1.0V in case of pulse width
20ns
3. Undershoot : -1.0V in case of pulse width
20ns
4. Overshoot and undershoot are sampled, not 100% tested.
POWER CONSUMPTION CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Max
Units
I
CC
1
Vcc operating
Cycle time=1s,100% duty
--
3
mA
supply current
I
OUT
=0mA,CE
0.2V,ZZ=V
IH
,
V
IN
0.2V or V
IN
Vcc-0.2V
I
CC
2
Vcc Dynamic operation
Cycle time=tRCmin,100% duty
--
20
mA
supply current
I
OUT
=0mA,CE
=
V
IL
,ZZ=V
IH
,
V
IN
=
V
IL
or V
IH
I
SB
1
TTL Standby Current
CE
=
V
IH
,ZZ=V
IH
,
--
0.3
mA
( TTL inputs )
Other inputs
=
V
IL
or V
IH
I
SB
2
CMOS Standby Current
CE
Vcc-0.2V,ZZ
Vcc-0.2V,
--
70
A
( CMOS inputs )
V
IN
0.2V or V
IN
Vcc-0.2V
I
ZZ
Deep power down mode
ZZ
0.2V,
--
25
A
V
IN
0.2V or V
IN
Vcc-0.2V
CAPACITANCE
Symbol
Parameter
Test Condition
Min
Max
Notes
C
IN
Input Capacitance
V
IN
=0V
-
8
pF
C
IO
Output Capacitance
V
IO
=0V
-
10
pF
6
Integrated Circuit Solution Inc.
PSR002-0A 02/05/2004
IC66LV10016AL
AC CHARATERISTICS
READ CYCLE
Symbol
Parameter
-70
Min
Max
Units
tRC
Read Cycle Time
70
32K
ns
tAA
Address Access time
--
70
ns
tOHA
Output Hold Time
5
--
ns
tACE
CE Access Time
--
70
ns
tDOE
OE Access Time
--
40
ns
tBA
UB, LB Access Time
--
25
ns
tASO
Address set up to OE Low
-5
--
ns
tASC
Address set up to CE Low
0
--
ns
tAHC
Address hold time from OE High
0
--
ns
tLZCE
CE to Low-Z Output
0
--
ns
tLZB
UB, LB to Low-Z Output
0
--
ns
tLZOE
OE to Low-Z Output
0
--
ns
tHZCE
CE to High- Z Output
--
15
ns
tHZB
UB, LB to High- Z Output
--
15
ns
tHZOE
OE to High-Z Output
--
15
ns
WRITE CYCLE
Symbol
Parameter
-70
Min
Max
Units
tWC
Write Cycle Time
70
32K
ns
tSCE
CE to Write End
60
--
ns
tSA
Address Setup Time
0
--
ns
tAW
Address Setup Time to Write End
60
--
ns
tASC
Address set up to CE Low
0
--
ns
tAHC
Address hold time from OE High
0
--
ns
tPWE
WE Pulse Width
40
--
ns
tPWB
LB, UB to End of Write
60
--
ns
tHA
Address Hold from Write End
0
--
ns
tSD
Data Setup to Write End
30
--
ns
tHD
Data Hold from Write End
0
--
ns
tCP
CE High Pulse width
30
--
ns
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Parameter
Value
Input pulse level
0.3 to Vcc-0.3V
Input rise and fall time
5ns
Input and output reference voltage
0.5V
CC
Output loads
CL=50pF+1TTL
1 TTL
50pF
Integrated Circuit Solution Inc.
7
PSR002-0A 02/05/2004
IC66LV10016AL
Power Down Cycle( Ta = -25~85
o
C)
Symbol
Parameter
Min
Max
Units
tSSP
CE High set up time for Power Down entry
0
--
ns
tSHP
CE High hold time before Power Down exit
0
--
ns
TC2LP
ZZ Low pulse width
30
--
ns
tHPD
CE High hold time after Power Down exit
300
--
s
Power Up Timing Requirement( Ta = -25~85
o
C)
Symbol
Parameter
Min
Max
Units
tSHU
CE ZZ set up time after Power Up
0
--
ns
tHPU
Standby hold time after Power Up
300
--
s
Data Retention Timing Requirement( Ta = -25~85
o
C)
Symbol
Parameter
Min
Max
Units
tBAH
A2 to A19 hold time during active
0
--
ns
tCSH
CE hold time for A2 to A19 fix
300
--
s
Address Skew Timing Requirement( Ta = -25~85
o
C)
Symbol
Parameter
Min
Max
Units
tSKEW
Maximum address skew
--
10
ns
8
Integrated Circuit Solution Inc.
PSR002-0A 02/05/2004
IC66LV10016AL
Power on
Initial State
Active Mode
Standby Mode
DPD Mode
CE=V
IH
Wait 200s
CE=V
IL ,
ZZ
=
V
IH
CE=V
IL
ZZ
=
V
IH
CE=V
IH
ZZ
=
V
IL
CE=V
IH
ZZ
=
V
IH
CE=V
IL
ZZ
=
V
IH
ZZ
=
V
IL
ZZ
=
V
IH
Standby Mode State machines
Standby Mode Characteristics
Mode
Memory Cell Data
Standby Current(A)
Wait Time(S)
Standby
Valid
70
0
DPD Mode
Invalid
25(I
ZZ
)
300
Integrated Circuit Solution Inc.
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PSR002-0A 02/05/2004
IC66LV10016AL
READ CYCLE
CE
OE
Data Out
Address
tRC
tOHA
tHZOE
tAA
tACE
tBA
tDOE
tLZOE
tLZB
tLZCE
tHZB
tHZCE
UB,LB
tASC
tASO
tAHC
WRITE CYCLE
(WE Control)
CE
WE
Data In
Address
t
W
C
tHA
tSA
tAW
tPWE
tSD
tHD
UB,LB
tSCE
tPWB
ZZ and WE must be H level for entire read cycle
ZZ and OE must be H level for entire read cycle
10
Integrated Circuit Solution Inc.
PSR002-0A 02/05/2004
IC66LV10016AL
WRITE CYCLE
(LB UB Control)
CE
WE
Data In
Address
t
W
C
tASC
tSA
tAW
tPWB
tSD
tHD
UB,LB
tSCE
tPWE
tHA
tAHC
ZZ and OE must be H level for entire read cycle
STANDBY
CE
Address
t
CP
tAHC
tASC
Standby
Active
Active
Integrated Circuit Solution Inc.
11
PSR002-0A 02/05/2004
IC66LV10016AL
Power Down Mode Entry / Exit
ZZ
CE
t
C2LP
tHPD
tSHP
tSSP
Power Up
VCC
ZZ
tSHU
tHPU
CE
VCC(min)
Data Retention(1)
CE
Address
(A
19
-A
2
)
t
BAH
Data Retention(2)
CE
Address
(A
19
-A
2
)
t
CSH
No Change
This applies for both read and write
This applies for both read and write
12
Integrated Circuit Solution Inc.
PSR002-0A 02/05/2004
IC66LV10016AL
Address Skew(1)
CE
A0-A19
t
RC / tWC
t
SKEN
tSKEN is from first address change to last address change
Address Skew(2)
CE
A0-A19
t
RC / tWC
t
SKEN
tSKEN is from first address change to last address change
Address Skew(2)
CE
A0-A19
t
SKEN
tSKEN is from first address change to last address change
Integrated Circuit Solution Inc.
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PSR002-0A 02/05/2004
IC66LV10016AL
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION
Temperature Range: -25C to +85C
Order Part No.
Speed (ns)
Package
IC66LV10016AL-70B
70
6*8mm TFBGA