iC-LA
64X1 LINEAR IMAGE SENSOR
Rev A2, Page 1/8
13.0mm 2.0mm
Q
D
C
A1
A0
A
Q
D
C
Q
D
C
A1
A0
A
Q
D
C
A1
A0
A
Q
D
C
VDDD
VDDD
VPIX
VTEMP
PIX(63)
TNH(63)
PIX(1)
TNH(1)
PIX(0)
TNH(0)
Pixel 63
Pixel 1
Pixel 0
EVEN
TNP
BIAS
POWER-DOWN-RESET
TEMP. SENSOR
A1
A0
A
A1
A0
A
A1
A0
A
Q
D
C
CLK
CLK
CLK
CLKD
CLKD
CLKD
CLKU
CLKU
CLKU
DOUT
DOUT
DOUT
DIND
DIND
DIND
DINU
DINU
DINU
VDDD
VDDD VDDA1
AOUT
CLK
DIN
DNU
DOUT
GNDA1
GNDD
VCMIN
iC-LA
CTH0
CTH1
CTH63
5V 5%
5V 5%
100nF
100
1k
+5V
Int.0
Int.1
Int.63
ODD
mux
GNDA2
VDDA2
100nF
VOLTAGE SOURCE
FEATURES
APPLICATIONS
64 photosensors with 200m pitch and an active area of
0.037mm
2
(ca. 183m x 200m)
Integrating amplifiers and track-and-hold feature
Low image lag
Integration time can be set externally
Internal bi-directional shift register
Extendable data I/O supports multiple sensor operation
On-chip temperature sensor
Detection of low supply voltage
TTL-/CMOS-compatible logic inputs and outputs
Single 5V operation, separate analog supply
Optical row sensors
CCD substitute
CHIP
BLOCK DIAGRAM
2001
iC-Haus GmbH
Tel. +49-6135-9292-0
Integrierte Schaltkreise
Fax +49-6135-9292-192
Am Kuemmerling 18, 55294 Bodenheim
http://www.ichaus.com
iC-LA
64X1 LINEAR IMAGE SENSOR
Rev A2, Page 2/8
DESCRIPTION
iC-LA is an integrating light-to-voltage converter with a row of 64 separate pixels. Each pixel consists of one
photodiode, an integration capacitor and a track-and-hold circuit. For each pixel the photocurrent of the
photodiode charges the integration capacitor. The track-and-hold circuit reads out the capacitor voltage in
track mode; when the circuit switches into hold mode this voltage is present for one clock cycle at output
AOUT.
Photocurrent integration is started simultaneously for all pixels with the rising edge of the clock signal if DIN
has received a high signal. Following hold mode, the pixels are subsequently selected by their output
switches. The downstream multiplexer selects the odd or even bus line for the output buffer. This dual line
configuration means that a high working speed is obtained.
The switches are controlled by the shift register whereas the multiplexer is operated by the control logic. The
DNU input signal determines the direction of shift. If DNU is low, the pixel signals are switched in ascending
order to AOUT, starting at pixel 0. If DNU is high, the pixels are switched in descending order, starting at pixel
63.
If input DIN is still high at the end of a completed integration cycle, all integration capacitors are automatically
reset and a new integration cycle is initiated. Continuous operation of the iC is thus possible.
All registers are reset with low voltage at the digital supply (power-down reset). All pins are protected against
damage by ESD.
iC-LA
64X1 LINEAR IMAGE SENSOR
Rev A2, Page 3/8
183
108
200
108
2000
108
13000
VDDA2
AOUT
DOUT
VDDD
GNDD
GNDA1
VDDA1
DIN
DNU
CLK
GNDA2
VCMIN
Pixel0
Pixel63
CHIP LAYOUT
dimensions in m; chip size 2.0mm 13.0mm
PAD DESCRIPTION
Name
Function
VDDA2
+5V Analog Supply Voltage 2
AOUT
Analog Output
GNDA2
Analog Ground 2
VCMIN
Offset Voltage Input for integration capacitor (connection to GNDA1, GNDA2 possible)
CLK
Clock Input
DNU
Down-Not-Up Input (pixel order is 0 to 63 when lo)
DIN
Data Input
DOUT
Data Output
VDDD
+5V Digital Supply Voltage
GNDD
Digital Ground
GNDA1
Analog Ground 1
VDDA1
+5V Analog Supply Voltage 1
External connections of VDDA1, VDDA2, VDDD to +5V and GNDA1, GNDA2, GNDD to 0V are required.
iC-LA
64X1 LINEAR IMAGE SENSOR
Rev A2, Page 4/8
All voltages are referenced to ground unless otherwise noted.
All currents into the device pins are positive; all currents out of the device pins are negative.
Fig. 1: typical relative spectral sensitivity, chip
(bandwidth 30nm)
Fig. 2: typical relative spectral sensitivity with
BMST assembly (bandwidth 30nm)
ABSOLUTE MAXIMUM RATINGS
Values beyond which damage may occur; device operation is not guaranteed.
Item
Symbol
Parameter
Conditions
Fig.
Unit
Nr.
Min.
Max.
G001 VDDA
Analog Supply Voltage
-0.3
6
V
G002 VDDD
Digital Supply Voltage
-0.3
6
V
G003 I(VDDA)
Current in VDDA
-25
25
mA
G004 I(VDDD)
Current in VDDD
-25
25
mA
G005 V()
Voltage at pins AOUT, VCMIN, CLK,
DNU, DIN, DOUT
-0.3
VDDA+0.3
V
G006 I()
Current in pins AOUT, VCMIN, CLK,
DNU, DIN, DOUT
-10
10
mA
E001 Vd()
ESD Susceptibility at all pins
MIL-STD-883, method 3015
HBM 100pF discharged over 1.5k
S
2
kV
TG1 Tj
Junction Temperature
-25
90
C
TG2 Ts
Storage Temperature
see package specification
THERMAL DATA
Operating Conditions: VDDA(1,2)= VDDD= 5V 5%, GNDA(1,2)= GNDD= 0V
Item
Symbol
Parameter
Conditions
Fig.
Unit
Nr.
Min.
Typ.
Max.
T1
Ta
Operating Ambient Temperature
Range
see package specification
C
ELECTRICAL and OPTICAL CHARACTERISTICS: Diagrams
iC-LA
64X1 LINEAR IMAGE SENSOR
Rev A2, Page 5/8
ELECTRICAL and OPTICAL CHARACTERISTICS
Operating Conditions: VDDA(1,2)= VDDD= 5V 5%, GNDA(1,2)= GNDD= 0V, Tj= -25..90C, unless otherwise noted
Item
Symbol
Parameter
Conditions
Tj
Fig.
Unit
Nr.
C
Min.
Typ.
Max.
Total Device
1
VDDA
Permissible Analog Supply
Voltage
4.75
5.25
V
2
VDDD
Permissible Digital Supply
Voltage
4.75
5.25
V
3
VCMIN
Permissible Offset Voltage for
Integration Capacitor
0
1
V
4
I(VDDA)
Supply Current in VDDA
15
20
mA
5
I(VDDD)
Supply Current in VDDD
f(CLK)
#
5 MHz
17
20
mA
6
I(VCMIN) Input Current in VCMIN
10
50
A
7
Vc()hi
Clamp Voltage hi at AOUT,
VCMIN, CLK, DNU, DIN, DOUT
Vc()hi= V(VDDA) - V();
I()= 1mA, other pins open
0.3
1.5
V
8
Vc()lo
Clamp Voltage lo at AOUT,
VCMIN, CLK, DNU, DIN, DOUT
Vc()lo= V(GNDA) - V();
I()= -1mA, other pins open
-1.5
-0.3
V
Analog Output AOUT
101
CL()
Permissible Load Capacitance
50
pF
102
Vs()lo
Saturation Voltage lo
I()= 1mA
300
400
mV
103
Vs()hi
Saturation Voltage hi
Vs()hi= VDDA - V(); I()= -1mA
400
mV
104
K1
Sensitivity
(naked chip)
8
= 880nm
8
= 660nm
8
= 550nm
8
= 470nm
3.48
6.46
3.69
3.20
4.19
7.78
4.44
3.85
4.74
8.79
5.02
4.35
V/pWs
V/pWs
V/pWs
V/pWs
105
KX
Sensitivity
(multi-chip BMST assembly)
8
= 880nm
8
= 660nm
8
= 550nm
8
= 470nm
3.35
6.22
3.55
3.08
4.19
7.78
4.44
3.85
5.03
9.34
5.33
4.62
V/pWs
V/pWs
V/pWs
V/pWs
106
)
K1
Sensitivity Nonuniformity
see note (1)
-7.5
7.5
%
107
V0()
Dark Voltage
referenced to VCMIN,
integration time is 200s
20
100
mV
108
V0()
Dark Voltage Deviation with
pixel in track mode
V0()= V0()t1 - V0()t2,
t= t2- t1 = 200s
-70
70
mV
109
V()
Output Voltage Deviation with
pixel in hold mode
V()= V()t1 - V()t2,
t= t2- t1 = 200s
-2
2
mV
110
V()
Output Voltage Linearity
(low level signal)
V()= V0()..0.75V; see note (2)
-7.5
7.5
mV
111
V()
Output Voltage Linearity
(high level signal)
V()= 0.75V..Vs()hi; see note (3)
-1
1
%
112
V0()rms
Output Voltage Noise (RMS)
V()= 0..4V, f(CLK)= 5MHz
2.5
mV
113
VT()
Temperature Voltage
V(CLK)= V(DIN)= 0V
25
2.9
3.1
3.25
V
114
VT()
Temperature Voltage Coefficient
V(CLK)= V(DIN)= 0V
-10
-9.5
-9
mV/C
Photosensor Characteristics
201
A()
Radiant Sensitive Area
183m x 200m per pixel
0.037
mm
2
202
S(
8
)max
Spectral Sensitivity
8
= 680nm
0.335
A/W
203
8
ar
Spectral Application Range
S(
8
ar)= 0.25 x S(
8
)max
400
950
mm
2
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