HD74HC673
16-bit Shift Register
Description
The HD74HC673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-
state input/output (data I/O) port to the shift register allows serial entry and/or reading of data. The storage
register is connected in a parallel data loop with the shift register and may be asynchronously cleared by
taking the store-clear input low. The storage register may be parallel loaded with shift-register data to
provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the
storage-register data upon command.
A high logic level at the chip-select (
CS) input disables both the shift-register clock and the storage register
clock and places the data I/O in the high-impedance state. The store-clear function is not disabled by the
chip select.
Caution must be exercised to prevent false clocking of either the shift register or the storage register via the
chip-select input. The shift clock should be low during the low-to-high transition of chip select and the
store clock should be low during the high-to-low transition of chip select.
Features
High Speed Operation: t
pd
(MODE/STRCLK to Y) = 23 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads (Q
15
output)
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 4 A max (Ta = 25C)
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