HD74HC195
4-bit Parallel-Access Shift Register
Description
This shift register features parallel inputs, parallel outputs, J-
K serial inputs, Shift/Load control input, and a
direct overriding clear. This shift register can operate in two modes: Parallel load; shift from Q
A
towards
Q
D
.
Paralle loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input
low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition
of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs
synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-
K
inputs. These inputs allow the first stage to perform as a J-
K or toggle flip-flop as shown in the function
table.
Features
High Speed Operation: t
pd
(Clock to Q) = 13 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
CC
(static) = 4 A max (Ta = 25C)
HD74HC195
2
Function Table
Inputs
Shift/
Serial
Parallel
Outputs
Clear Load Clock J
K
A
B
C
D
Q
A
Q
B
Q
C
Q
D
Q
D
L
X
X
X
X
X
X
X
X
L
L
L
L
H
H
L
X
X
a
b
c
d
a
b
c
d
d
H
H
L
X
X
X
X
X
X
Q
A0
Q
B0
Q
C0
Q
D0
Q
D0
H
H
L
H
X
X
X
X
Q
A0
Q
A0
Q
Bn
Q
Cn
Q
Cn
H
H
L
L
X
X
X
X
L
Q
An
Q
Bn
Q
Cn
Q
Cn
H
H
H
H
X
X
X
X
H
Q
An
Q
Bn
Q
Cn
Q
Cn
H
H
H
L
X
X
X
X
Q
An
Q
An
Q
Bn
Q
Cn
Q
Cn
H :
high level (steady state)
L
:
low level (steady state)
X :
don't care
:
transition from low to high level.
a, b, c, d
:
the level of steady-state input at inputs A, B, C or D respectively.
Q
A0
, Q
B0
, Q
C0
, Q
D0
:
the level of Q
A
, Q
B
, Q
C
or Q
D
respectively, before the indicated steady-state input
conditions were established.
Q
An
, Q
Bn
, Q
Cn
, Q
Dn
:
the level of Q
A
, Q
B
, Q
C
or Q
D
respectively before the most recent
transition of
the clock.
PDF 
ZIP
