927
HD66503
(240-Channel Common Driver with Internal LCD
Timing Circuit)
Description
The HD66503 is a common driver for liquid crystal dot-matrix graphic display systems. This device
incorporates a 240 liquid crystal driver and an oscillator, and generates timing signals (alternating signals
and frame synchronizing signals) required for the liquid crystal display. It also achieves low current
consumption of 100 A through the CMOS process. Combined with the HD66520, a 160-channel column
driver with an internal RAM, the HD66503 is optimal for use in displays for portable information tools.
Features
LCD timing generator: 1/120, 1/240 duty cycle internal generator
Alternating signal waveform generator: Pin programmable 2 to 63 line inversion
Recommended display duty cycle: 1/120, 1/240 (master mode): 1/120 to 1/240 (slave mode)
Number of LCD driver: 240
Power supply voltage: 2.7 to 5.5V
High voltage: 8 to 28-V LCD drive voltage
Low power consumption: 100 A (during display)
Internal display off function
Oscillator circuit with standby function: 130 kHz (max)
Display timing operation clock: 65 kHz (max) (operating at 1/2 system clock)
Package: 272-pin TCP
CMOS process
Ordering Information
Type No.
TCP
Outer Lead Pitch (m)
HD66503TA0
Straight TCP
200
HD66503TB0
Folding TCP
200
HD66503
928
Pin Arrangement
272
V2R
271
V5R
270
V6R
269
V1R
268
V
EER
267
V
CC2
266
M/S
265
DOC
264
FLM
263
CL1
262
M
261
RESET
260
DISPOFF
259
DUTY
258
MEOR
257
MWS0
256
MWS1
255
MWS2
254
MWS3
253
MWS4
252
MWS5
251
SHL
250
GND
249
C
248
R
247
CR
246
V
CC1
245
V
EEL
244
V1L
243
V6L
242
V5L
241
V2L
X240
1
X239
2
X238
3
X237
4
X236
5
X235
6
X234
7
X233
8
X232
9
X231
10
X10
231
X9
232
X8
233
X7
234
X6
235
X5
236
X4
237
X3
238
X2
239
X1
240
Top View
Note : This figure does not specify the tape carrier package dimensions.
HD66503
929
Pin Description
Classi-
fication
Symbol
Pin No.
Pin Name
I/O
Number
of Pins Functions
Power
supply
V
CC1
,
V
CC2
246
267
V
CC
Power
supply
2
V
CC
GND: logic power supply
GND
250
GND
Power
supply
1
V
EEL
,
V
EER
245
268
V
EE
Power
supply
2
V
CC
V
EE
: LCD drive circuits power supply
V1L, R
V2L, R
V5L, R
V6L, R
244
269
241
272
242
271
243
270
V1
V2
V5
V6
Input
Input
Input
Input
2
2
2
2
LCD drive level power supply
See Figure 1.
Control
signals
M/
6
266
Master/slave Input
1
Controls the initiation and termination of
the LCD timing generator. In addition,
the input/output is determined of 4 signal
pins: display data transfer clock (CL1);
first line marker (FLM); alternating signal
(M); and display off control (
'2&
). See
Table 1 for details.
DUTY
259
Duty
Input
1
Selects the display duty cycle.
Low level: 1/120 display duty ratio
High level:
1/240 display duty ratio
MWS0 to
MWS5
257
256
255
254
253
252
MWS0
MWS1
MWS2
MWS3
MWS4
MWS5
Input
6
The number of line in the line alternating
waveform is set during master mode.
The number of lines can be set between
10 and 63.
When using the external alternating
signal or during slave mode, set the
number of lines to 0. See Table 2.
MEOR
258
M Exclusive-
OR
Input
1
During master mode, the signals
alternating waveform output from pin M
is selected.
During low level, the line alternating
waveform is output from pin M.
During high level, pin M outputs an
EOR (exclusive OR) waveform between
a line alternating waveform and frame
alternating waveform. Set the pin to low
during slave mode. See Table 3.
HD66503
930
Classi-
fication
Symbol
Pin No.
Pin Name
I/O
Number
of Pins
Functions
Control
signals
CR, R, C
247
248
249
CR
R
C
3
These pins are used as shown in Figure
4 in master mode, and as shown in
Figure 5 in slave mode.
5(6(7
261
Reset
Input
1
The following initiation will be proceeded
by setting to initiation.
1) Stops the internal oscillator or the
external oscillator clock input.
2) Initializes the counters of the liquid
crystal display timing generator and
alternating signal (M) generator.
3) Set display off control output (
'2&
)
to low and turns off display.
After reset, display off control output
(
'2&
) will stay low for four more frame
cycles (four clocks of FLM signals) to
prevent error display at initiation. The
electrical characteristics are shown in
Table 4. See Figure 2.
However, when reset is performed
during operation, RAM data in the
HD66520 which is used together with
the HD66503 may be destroyed.
Therefore, write data to the RAM again.
LCD
timing
CL1
263
Clock 1
I/O
1
The bidirectional shift register shifts
data at the falling edge of CL1. During
master mode, this pin-outputs a data
transfer clock with a two times larger
cycle than the internal oscillator (or the
cycle of the external clock) with a duty
of 50%. During slave mode, this pin
inputs the external data transfer clock.
FLM
264
First line
marker
I/O
1
During master mode, pin FLM outputs
the first line marker. During slave mode,
this pin inputs the external data first line
marker. The shift direction of the first
line marker is determined by DUTY and
SHL signal as follows. Set signal DUTY
to high during slave mode. See Table 5.
M
262
M
I/O
1
Pin M inputs and outputs the alternating
signal of the LCD output.
HD66503
931
Classi-
fication
Symbol
Pin No.
Pin Name
I/O
Number
of Pins
Functions
LCD
timing
SHL
251
Shift left
Input
1
Pin SHL switches the shift direction of
the shift register. Refer to FLM for
details.
',632))
260
Display off
Input
1
Turns off the LCD.
During master mode, liquid crystal drive
output X1 to X240 can be set to level
V1 by setting the pin to low. By setting
the HD66520 to level V1 in the same
way, the data on the display can be
erased. During slave mode, set
',632))
high.
'2&
265
Display off
control
I/O
1
Controls the display-off function. During
master mode, pin
'2&
becomes an
output pin and controls display off after
reset and display off according to signal
',632))
. In this case, connect this
signal to the HD66520's pin
',632))
.
During slave mode, pin
'2&
becomes
an input pin for display off control
signal. In this case, connect this signal
to the master HD66503's pin
'2&
.
LCD
drive
output
X1 to
X240
240
to 1
X1 to
X240
Output 240
Selects one from among four levels
(V1, V2, V5, and V6) depending on the
combination of M signal and display
data. See Figure 3.
Note: 30 input/outputs (excluding driver block)
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