S7199
S7199 is a family of FFT-CCD image sensors specifically designed for X-ray imaging. FOS (Fiber Optic plate with Scintillator) that
converts X-ray into visible-light is mounted on a CCD chip, which enables S7199 to do the X-ray imaging. Two CCD chips of
symmetric from side to side are mounted closely for realizing the possible minimum dead space in between. The effective
photosensitive length of about 150 mm in total is realized; each chip has 1536 128 channels, and 48 48 m is a pixel size.
Even a X-ray image of moving object can be taken by taking a unique operation method of TDI, which can also be useful for a
non-destructive test where the object moves on a belt conveyer.
The each chip of S7199 has an effective pixel size of 48 48 m and is available in active area of 73.728 (H) 6.144 (V) mm
2
.
Features
l 1536 (H) 128 (V) pixel format
l Pixel size: 48 48 m
l Buttable structure of 2 chips
l Coupled with FOS for X-ray imaging
l TDI (Time Delay Integration) operation
l 100 % fill factor
l Wide dynamic range
l Low dark signal
l Low readout noise
l MPP operation
Applications
l General X-ray imaging
l Non-destructive inspection
l Dental panorama
I M A G E S E N S O R
CCD area image sensor
Front-illuminated FFT-CCDs for X-ray imaging
I Selection guide
Type No.
Cooling
Number of
total pixels
Number of
active pixels
Active area
[mm (H) mm(V)]
S7199
Non-cooled
1536 128
1536 128
73.728 6.144
Note) As an input window, FOS is suited to S7199.
I General ratings
Parameter
Specification
CCD structure
Full frame transfer or TDI
Fill factor
100 %
Number of active pixels
1536 (H) 128 (V) *
1
Pixel size
48 (H) 48 (V) m
CCD active area
73.728 (H) 6.144 (V) mm *
1
X-ray sensitive area
146 6 mm
Vertical clock phase
2 phase and 2 line
Horizontal clock phase
2 phase and 2 line
Output circuit
Two-stage MOSFET source follower with load resistance
Package
40 pin ceramic package
Window
FOS (Fiber Optic plate with Scintillator)
*1: Number of active pixels per chip. Two chips are used.
1
CCD area image sensor
S7199
I Absolute maximum ratings (Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Storage temperature
Tstg
-10
-
+70
C
Operating temperature
Topr
0
-
+40
C
OD voltage
V
OD
-0.5
-
+20
V
RD voltage
V
RD
-0.5
-
+18
V
ISV voltage
V
ISV
-0.5
-
+18
V
IGV voltage
V
IGV
-10
-
+15
V
IGH voltage
V
IGH
-10
-
+15
V
SG voltage
V
SG
-10
-
+15
V
OG voltage
V
OG
-10
-
+15
V
RG voltage
V
RG
-10
-
+15
V
TG voltage
V
TG
-10
-
+15
V
Vertical clock voltage
V
P1AV
, V
P2AV
V
P1BV
, V
P2BV
-10
-
+15
V
Horizontal clock voltage
V
P1AH
, V
P2AH
V
P1BH
, V
P2BH
-10
-
+15
V
I Operating conditions (MPP mode, Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output transistor drain voltage
V
OD
12
15
18
V
Reset drain voltage
V
RD
11.5
12
12.5
V
Output gate voltage
V
OG
1
3
5
V
Output transistor ground voltage
V
SSA
-
0
-
V
Substrate voltage
V
SSD
-5
0
-
V
Vertical input source
V
ISV
-
V
RD
-
Vertical input gate
V
IGV
-8
0
-
Test point
Horizontal input gate
V
IGH
-8
0
-
V
High
V
P1AVH
, V
P2AVH
V
P1BVH
, V
P2BVH
4
6
8
Vertical shift register
clock voltage
Low
V
P1AVL
, V
P2AVL
V
P1BVL
, V
P2BVL
-9
-8
-7
V
High
V
P1AHH
, V
P2AHH
V
P1BHH
, V
P2BHH
4
6
8
Horizontal shift register
clock voltage
Low
V
P1AHL
, V
P2AHL
V
P1BHL
, V
P2BHL
-9
-8
-7
V
High
V
SGH
4
6
8
Summing gate voltage
Low
V
SGL
-9
-8
-7
V
High
V
RGH
4
6
8
Reset gate voltage
Low
V
RGL
-9
-8
-7
V
High
V
TGH
4
6
8
Transfer gate voltage
Low
V
TGL
-9
-8
-7
V
I Electrical characteristics (Ta=25 C)
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Signal output frequency
fc
-
2
4
MHz
Reset clock frequency
frg
-
2
4
MHz
Vertical shift register capacitance
C
P1AV
, C
P2AV
C
P1BV,
C
P2BV
-
15000
-
pF
Horizontal shift register capacitance
C
P1AH
, C
P2AH
C
P1BH
, C
P2BH
-
500
-
pF
Summing gate capacitance
C
SG
-
15
-
pF
Reset gate capacitance
C
RG
-
10
-
pF
Transfer gate capacitance
C
TG
-
500
-
pF
Transfer efficiency
CTE
*
2
0.99995
0.99999
-
DC output level
Vout
*
3
5
8
11
V
Output impedance
Zo
*
3
-
500
-
9
Power dissipation
P
*
3,
*
4
-
60
-
mW
*2: Measured at half of the full well capacity. CTE is defined per pixel.
*3: V
OD
=15 V.
*4: Power dissipation of the on-chip amplifier (each chip).
2
CCD area image sensor
S7199
......
1
2
3
4
5
6
23
4
125
126
127
128
S1
S2
S3
S4
S5
S6
S1531
S1532
S1533
S1534
S1535
S1536
......
......
1531
1532
1533
1534
1535
1536
ISV A14
A15
IGV
P1BV
P2BV
P1AV
P2AV
TG
RG
RD
SSA
OS
OD
OG
SG
P2AH
P1AH
P2BH P1BH IGH
SSD
......
1
2
3
4
5
6
23
4
125
126
127
128
S1
S2
S3
S4
S5
S6
S1531
S1532
S1533
S1534
S1535
S1536
......
......
1531
1532
1533
1534
1535
1536
P2AH
P1AH
P2BH
P1BH
IGH
SSD
LEFT CHIP
RIGHT CHIP
S1, ... , S1536: ACTIVE ELEMENTS
S1, ... , S1536: ACTIVE ELEMENTS
A16
A17
A18
A19
A20
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 A12 A13
B1
B2
B3
B4
B5
B6
ISV
IGV
P1BV
P2BV
P1AV
P2AV
TG
RG
RD
SSA
OS
OD
OG
SG
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
I Electrical and optical characteristics (Ta=25 C, unless otherwise noted)
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Saturation output voltage
Vsat
-
Fw Sv
-
V
Full well capacity
Fw
600
1200
-
ke
-
CCD node sensitivity
Sv
*
5
0.3
0.55
-
V/e
-
Dark current (MPP mode)
DS
*
6
-
8
24
ke
-
/pixel/s
Readout noise
Nr
*
7
-
60
120
e
-
rms
Dynamic range
DR
*
8
5,000
20,000
-
X-ray response non-uniformity
XRNU
*
9,
*
10
-
20
30
%
White spots
-
-
10
Point
defects *
11
Black spots
-
-
10
Cluster defects
*
12
-
-
0
Blemish
Column defects
-
*
13
-
-
0
-
*5: V
OD
=15 V.
*6: Dark current doubles for every 5 to 7 C.
*7: -40 C, operating frequency is 2 MHz.
*8: Dynamic range = Full well capacity / Readout noise
*9: X-ray irradiation of 60kVp, measured at half of the full well capacity.
*10: XRNU (%) = Noise / Signal 100
Noise: Fixed pattern noise (peak to peak)
Measuring region that is within 146.0 mm (H) 6.0 mm (V) (refer to dimensional outline)
*11: White spots > 20 times of typ. dark signal (8 ke
-
/pixel/s).
Black spots > 50 % reduction in response relative to adjacent pixels, measured at half of the full well capacity.
*12: continuous 2 to 9 point defects.
*13: continuous >10 point defects.
I Device structure
KMPDC0110EA
I Pixel format
Left Horizontal Direction Right
Blank
Optical
black
Isolation
Effective
Isolation
Optical
black
Blank
0
0
0
15360
0
0
Top Vertical direction Bottom
Isolation
Effective
Isolation
0
128
0
3
CCD area image sensor
S7199
I Pin connections
Pin No.
Symbol
Description
Remark
A1
RG
Reset gate
A2
RD
Reset drain
A3
SSA
Analog ground
A4
OS
Output transistor source
A5
OD
Output transistor drain
A6
OG
Output gate
A7
SG
Summing gate
A8
P2AH
CCD horizontal register clock A-2
A9
P1AH
CCD horizontal register clock A-1
A10
SSD
Digital ground
A11
P2BH
CCD horizontal register clock B-2
Same timing as P2AH
A12
P1BH
CCD horizontal register clock B-1
Same timing as P1AH
A13
IGH
Test point (Horizontal input gate)
A14
ISV
Test point (Vertical input source)
Shorted to RD
A15
IGV
Test point (Vertical input gate)
A16
P1BV
CCD vertical register clock B-1
Same timing as P1AV
A17
P2BV
CCD vertical register clock B-2
Same timing as P2AV
A18
P1AV
CCD vertical register clock A-1
A19
P2AV
CCD vertical register clock A-2
A20
TG
Transfer gate
B1
IGH
Test point (Horizontal input gate)
B2
P1BH
CCD horizontal register clock B-1
Same timing as P1AH
B3
P2BH
CCD horizontal register clock B-2
Same timing as P2AH
B4
SSD
Digital ground
B5
P1AH
CCD horizontal register clock A-1
B6
P2AH
CCD horizontal register clock A-2
B7
SG
Summing gate
B8
OG
Output gate
B9
OD
Output transistor drain
B10
OS
Output transistor source
B11
SSA
Analog ground
B12
RD
Reset drain
B13
RG
Reset gate
B14
TG
Transfer gate
B15
P2AV
CCD vertical register clock A-2
B16
P1AV
CCD vertical register clock A-1
B17
P2BV
CCD vertical register clock B-2
Same timing as P2AV
B18
P1BV
CCD vertical register clock B-1
Same timing as P1AV
B19
IGV
Test point (Vertical input gate)
B20
ISV
Test Point (Vertical input source)
Shorted to RD
I Precautions for use (Electrostatic countermeasures)
* Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with
an earth ring, in order to prevent electrostatic damage due to electrical charges from friction.
* Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge.
* Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to
discharge.
* Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to
the amount of damage that occurs.
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, http://www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658
France: Hamamatsu Photonics France S.A.R.L.: 8, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Smidesvgen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions.
Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. 2003 Hamamatsu Photonics K.K.
Cat. No. KMPD1047E07
Apr. 2003 DN
6
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