S7017 series is a family of FFT-CCD area image sensors specifically designed for low-light-level detection in scientific applications. By using the
binning operation, S7017 series can be used as a linear image sensor having a long aperture in the direction of the device length. This makes
S7017 series ideally suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal processing
speed compared with conventional methods by which signals are digitally added by an external circuit. S7017 series also features low noise and
low dark signal (MPP mode operation). These enable low-light-level detection and long integration time, thus achieving a wide dynamic range.
S7017 series has a pixel size of 24 24
m and is available in active area of 24.576 (H) 2.976 (V) and 24.576 (H) 6.048 (V) mm.
A four-stage Peltier element is built into the same package for thermoelectric cooling. At room temperature operation, the device can be cooled
down to -70 C with using forced air cooling. In addition, since both the CCD chip and Peltier element are hermetically sealed, no dry air is
required, thus allowing easy handling.
Features
Applications
I M A G E S E N S O R
CCD area image sensor
Four-stage TE-cooled, front-illuminated FFT-CCDs
S7017 series
I Selection and order guide
Type No.
Cooling
Number of
total pixels
Number of
active pixels
Active area
[mm (H) mm (V)]
S7017-1007
1044 128
1024 124
24.576 2.976
S7017-1008
Four-stage
TE-cooled
1044 256
1024 252
24.576 6.048
S7017 series has a hermetically-sealed package with AR-coated sapphire window.
I General ratings
Parameter
Specification
CCD structure
Full frame transfer
Fill factor
100 %
Number of active pixels
S7017-1007: 1024 (H) 124 (V)
S7017-1008: 1024 (H) 252 (V)
Pixel size
24 (H) 24 (V) m
Active area
S7017-1007: 24.576 (H) 2.976 (V) mm
S7017-1008: 24.576 (H) 6.048 (V) mm
Vertical clock phase
2 phase
Horizontal clock phase
2 phase
Output circuit
One-stage MOSFET source follower
Package
28 pin metal package
Window
AR coated Sapphire
G 1024 (H) 124 (V) and 1024 (H) 252 (V) pixel format
G Pixel size: 24 24 m
G 100 % fill factor
G Wide dynamic range
G Low dark current
G Low readout noise
G MPP operation
G Four-stage TE-cooled
G Astronomy
G Scientific measuring instrument
G Fluorescence spectrometer
G Raman spectrophotometer
G Optical and spectrophotometric analyzer
G For low-light-level detection requiring
1
CCD area image sensor
S7017 series
I Absolute maximum ratings (Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating temperature
Topr
-50
-
+30
C
Storage temperature
Tstg
-100
-
+70
C
OD voltage
V
OD
-0.5
-
+25
V
RD voltage
V
RD
-0.5
-
+18
V
ISV voltage
V
ISV
-0.5
-
+18
V
ISH voltage
V
ISH
-0.5
-
+18
V
IGV voltage
V
IG1V
, V
IG2V
-10
-
+15
V
IGH voltage
V
IG1H
, V
IG2H
-10
-
+15
V
SG voltage
V
SG
-10
-
+15
V
OG voltage
V
OG
-10
-
+15
V
RG voltage
V
RG
-10
-
+15
V
TG voltage
V
TG
-10
-
+15
V
Vertical clock voltage
V
P1V
, V
P2V
-10
-
+15
V
Horizontal clock voltage
V
P1H
, V
P2H
-10
-
+15
V
I Operating conditions (MPP mode, Ta=25 C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output transistor drain voltage
V
OD
18
20
22
V
Reset drain voltage
V
RD
11.5
12
12.5
V
Output gate voltage
V
OG
1
3
5
V
Substrate voltage
V
SS
-
0
-
V
Test point (vertical input source)
V
ISV
-
V
RD
-
V
Test point (horizontal input source)
V
ISH
-
V
RD
-
V
Test point (vertical input gate)
V
IG1V
, V
IG2V
-8
0
-
V
Test point (horizontal input gate)
V
IG1H
, V
IG2H
-8
0
-
V
High
V
P1VH
, V
P2VH
4
6
8
Vertical shift register
clock voltage
Low
V
P1VL
, V
P2VL
-9
-8
-7
V
High
V
P1HH
, V
P2HH
4
6
8
Horizontal shift register
clock voltage
Low
V
P1HL
, V
P2HL
-9
-8
-7
V
High
V
SGH
4
6
8
Summing gate voltage
Low
V
SGL
-9
-8
-7
V
High
V
RGH
4
6
8
Reset gate voltage
Low
V
RGL
-9
-8
-7
V
High
V
TGH
4
6
8
Transfer gate voltage
Low
V
TGL
-9
-8
-7
V
I Electrical characteristics (Ta=25 C)
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Signal output frequency
fc
-
-
80
2,000
kHz
Reset clock frequency
frg
-
-
80
2,000
kHz
S7017-1007
-
-
3,200
-
Vertical shift register
capacitance
S7017-1008
C
P1V
, C
P2V
-
-
6,400
-
pF
Horizontal shift register capacitance
C
P1H
, C
P2H
-
-
300
-
pF
Summing gate capacitance
C
SG
-
-
7
-
pF
Reset gate capacitance
C
RG
-
-
7
-
pF
Transfer gate capacitance
C
TG
-
-
150
-
pF
Transfer efficiency
CTE
*
1
0.99995
0.99999
-
-
DC output level
Vout
*
2
12
15
18
V
Output impedance
Zo
*
2
-
3
-
kW
Power dissipation
P
*
2,
*
3
-
15
-
mW
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: V
OD
=20 V , Load resistance=22 kW
*3: Power dissipation of the on-chip amplifier.
2
CCD area image sensor
S7017 series
IElectrical and optical characteristics (Ta=25 C, unless otherwise noted)
Parameter
Symbol
Remark
Min.
Typ.
Max.
Unit
Saturation output voltage
Vsat
-
-
Fw Sv
-
V
Vertical
150
300
-
Full well
capacity
Horizontal
Fw
*
"
300
600
-
ke-
CCD conversion efficiency
Sv
*
#
1.8
2.2
-
V/e-
+25 C
-
400
3,000
0 C
-
20
150
Dark current
(MPP mode)
-70 C
DS
*
$
-
0.0015
0.01
e-/pixel/s
Readout noise
Nr
*
%
-
6
12
e-rms
Line binning
25,000
75,000
-
Dynamic range
Area scanning
DR
*
&
12,500
37,500
-
-
Spectral response range
l
-
-
400 to 1,100
-
nm
Photo response non-uniformity
PRNU
*
'
-
-
10
%
Point defects
*
-
-
0
Cluster defects
*
-
-
0
Blemish
Column defects
-
*
-
-
0
-
*4: Large horizontal full well for line binning operation.
*5: V
OD
=20 V , Load resistance=22 kW
*6: Dark current nearly doubles for every 5 to7 C increase in temperature.
*7: -40 C, operating frequency is 80 kHz.
*8: DR = Fw / Nr
*9: Measured at half of the full well capacity. PRNU (%) = noise / signal 100, noise: fixed pattern noise (peak to peak)
*10: White spots > 3 % of full well at 0 C after Ts=1 s, Black spots > 50 % reduction in response relative to adjacent
pixels
*11: continuous 2 to 9 point defects
*12: continuous >10 point defects
I PIN connections
Pin No.
Symbol
Description
Remark
1
P-
TE-cooler-
2
NC
3
SS
Substrate (GND)
4
NC
5
ISV
Test point (vertical input source)
Shorted to RD
6
IG2V
Test point (vertical input gate-2)
Shorted to 0 V
7
IG1V
Test point (vertical input gate-1)
Shorted to 0 V
8
RG
Reset gate
9
RD
Reset drain
10
OS
Output transistor source
11
OD
Output transistor drain
12
OG
Output gate
13
SG
Summing gate
Same timing as P2H
14
P+
TE-cooler+
15
TSH1
Temperature sensor (hot side)
16
TSC1
Temperature sensor (cool side)
17
TSC2
Temperature sensor (cool side)
18
P2H
CCD horizontal register clock-2
19
P1H
CCD horizontal register clock-1
20
IG2H
Test point (horizontal input gate-2)
Shorted to 0 V
21
IG1H
Test point (horizontal input gate-1)
Shorted to 0 V
22
ISH
Test point (horizontal input source)
Shorted to RD
23
P2V
CCD vertical register clock-2
24
P1V
CCD vertical register clock-1
25
TG
Transfer gate
Same timing as P2V *
!
26
NC
27
NC
28
TSH2
Temperature sensor (hot side)
*13: TG is an isolation gate between vertical register and horizontal resister.
In standard operation, the same pulse of P2V should be applied to the TG.
3
CCD area image sensor
S7017 series
50
40
30
20
10
0
400
500
600
700
WAVELENGTH (nm)
800
900
1000 1100 1200
QUANTUM EFFICIENCY (%)
(Typ. Ta=25 C)
KMPDB0051EA
I Spectral response without window
100
(Typ. Ta=25 C)
95
90
85
80
400
500
600
700
800
WAVELENGTH (nm)
TRANSMITT
ANCE (%)
900
1000 1100 1200
AR COATED SAPPHIRE
KMPDB0106EA
KMPDA0098EA
I Dimensional outline (unit: mm)
4.0
7.0
5.0
PINCHED OFF TUBE
S7017-1007
TYPE No.
24.576 (H)
a
S7017-1008 24.576 (H)
2.976 (V)
b
ACTIVE AREA
6.048 (V)
2.54
27.94
0.46
20.0
b
36.0
44.0
50.0
35.0
6.4 0.5
18.5 0.5
47.0
50.8
0.25
14
13
12
3
2
16
17
26
27
a
1.0
PIN No. 1
1st PIN INDEX MARK
AR-COATED SAPPHIRE WINDOW
15
28
I Spectral transmittance characteristic
of window material
4
CCD area image sensor
S7017 series
KMPDC0085EA
I Device structure, line output format
......
......
......
V
1
H
IG1V IG2V ISV
SS
RG
RD
OS
OD
OG
SG
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
S1
S2
S1023
S1024
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
8
9
10
11
12
13
3
6
5
7
25
24
V=124, 252
H=1024
ISH
IG1H
IG2H
P1H
P2H
22
21
20
19
18
4 BLANK
4 BLANK
4 OPTICAL
BLACK
4 OPTICAL
BLACK
1024
SIGNAL OUT
2 ISOLATOIN
2 ISOLATOIN
TG
P1V
23
P2V
KMPDC0086EA
I Timing chart
G Area scanning 1 (low dark current mode)
INTEGRATION PERIOD
(Shutter must be open)
P1V
RG
OS
P2V, TG
P1H
P2H, SG
READOUT PERIOD (Shutter must be closed)
ENLARGED VIEW
4..127
4..255
128
124+4 (ISOLATION)
256
252+4 (ISOLATION)
: S7017-1007
: S7017-1008
Tpwv
Tovr
Tpwr
D1
D2
D3
D4
D18
D19
D20
D5..D10, S1..S1024, D11..D17
P2V, TG
P1H
P2H, SG
RG
OS
Tpwh, Tpws
1
2
3
Pixel format
Left Horizontal Direction Right
Blank
Optical Black
Isolation
Effective
Isolation
Optical Black
Blank
4
4
2
1024
2
4
4
Top Vertical Direction Bottom
Isolation
Effective
Isolation
2
124 or 252
2
5
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