Rev: 1.01 3/2002
1/44
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS88218/36AB/D-250/225/200/166/150/133
512K x 18, 256K x 36
9Mb SCD/DCD Sync Burst SRAMs
250 MHz
133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119- and 165-Bump BGA
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip read parity checking; even or odd selectable
ZQ mode pin for user-selectable high/low output drive
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 165-bump BGA packages
Functional Description
Applications
The GS88218/36A is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS88218/36A is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS88218/36A operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr
(x18)
Curr
(x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
Rev: 1.01 3/2002
2/44
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36AB/D-250/225/200/166/150/133
165 Bump BGA--x18 Commom I/O--Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
B
B
NC
E3
BW
ADSC
ADV
A
A18
A
B
NC
A
E2
NC
B
A
CK
GW
G
ADSP
A
NC
B
C
NC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPA
C
D
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
D
E
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
E
F
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
F
G
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
G
H
FT
MCL
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZQ
ZZ
H
J
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
J
K
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
K
L
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
L
M
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
M
N
DQPB
SCD
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
NC
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
A17
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
Rev: 1.01 3/2002
3/44
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36AB/D-250/225/200/166/150/133
165 Bump BGA--x36 Common I/O--Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
B
C
B
B
E3
BW
ADSC
ADV
A
NC
A
B
NC
A
E2
B
D
B
A
CK
GW
G
ADSP
A
NC
B
C
DQPC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPB
C
D
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
D
E
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
E
F
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
F
G
DQC
DQC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQB
DQB
G
H
FT
MCL
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZQ
ZZ
H
J
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
J
K
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
K
L
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
L
M
DQD
DQD
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
DQA
M
N
DQPD
SCD
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
DQPA
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
A17
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
Rev: 1.01 3/2002
4/44
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36AB/D-250/225/200/166/150/133
GS88218/36 165-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
R6, P6
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A2, A10, B2, B10, P3, P4, P8, P9,
P10, R3, R4, R8, R9, R10, R11
An
I
Address Inputs
P11
A
17
Address Input
A11
A
18
I
Address Input (x18 Version)
J10, K10, L10, M10, J11, K11, L11,
M11, N11
G10, F10, E10, D10, G11, F11,
E11, D11, C11
G2, F2, E2, D2, G1, F1, E1, D1, C1
J2, K2, L2, M2, J1, K1, L1, M1, N1
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
I/O
Data Input and Output pins. (x36 Version)
B5, A5, A4, B4
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low (x36 Version)
M10, L10, K10, J10, G11, F11, E11,
D11, C11
D2, E2, F2, G2, J1, K1, L1, M1, N1
DQ
A1
DQ
A9
DQ
C1
DQ
C9
I/O
Data Input and Output pins (x18 Version)
B5, A4
B
A
, B
C
I
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low (x18 Version)
A1, B1, B11, C2, C10, H3, H9, N5,
N6, N7, N10, P1, P2, R2
NC
--
No Connect
A5, B4, C1, D1, D10, E1, E10, F1,
F10, G1, G10, J2, J11, K2, K11, L2,
L11, M2, M11, N11
NC
--
No Connect (x18 Version)
A11
NC
--
No Connect (x36 Version)
B6
CK
I
Clock Input Signal; active high
A7
BW
I
Byte Write--Writes all enabled bytes; active low
B7
GW
I
Global Write Enable--Writes all bytes; active low
A3
E
1
I
Chip Enable; active low
A6
E
3
I
Chip Enable; active low (x36 version)
B3
E
2
I
Chip Enable; active high (x36 version)
B8
G
I
Output Enable; active low
A9
ADV
I
Burst address counter advance enable; active l0w
A8, B9
ADSC, ADSP
I
Address Strobe (Processor, Cache Controller); active low
H11
ZZ
I
Sleep mode control; active high
H1
FT
I
Flow Through or Pipeline mode; active low
R1
LBO
I
Linear Burst Order mode; active low
H10
ZQ
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive],
High = High Impedance [Low Drive])
R5
TMS
I
Scan Test Mode Select
P5
TDI
I
Scan Test Data In
Rev: 1.01 3/2002
5/44
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88218/36AB/D-250/225/200/166/150/133
P7
TDO
O
Scan Test Data Out
R7
TCK
I
Scan Test Clock
H2
MCL
--
Must Connect Low
N2
SCD
--
Single Cycle Deselect/Dual Cyle Deselect Mode Control
D4, D8, E4, E8, F4, F8, G4, G8, H4,
H8, J4, J8, K4, K8, L4, L8, M4, M8
V
DD
I
Core power supply
C4, C5, C6, C7, C8, D5, D6, D7,
E5, E6, E7, F5, F6, F7, G5, G6, G7,
H5, H6, H7, J5, J6, J7, K5, K6, K7,
L5, L6, L7, M5, M6, M7, N4, N8
V
SS
I
I/O and Core Ground
C3, C9, D3, D9, E3, E9, F3, F9, G3,
G9, J3, J9, K3, K9, L3, L9, M3, M9,
N3, N9
V
DDQ
I
Output driver power supply
GS88218/36 165-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
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