GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: February 2002
Document No. 22612 - 0
PRODUCT BRIEF
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FEATURES
FEATURES
FEATURES
FEATURES
compliant with SMPTE 292M and SMPTE 259M-C
DVB-ASI auto-configuration
DVB-ASI sync word detection and 8b/10b decoding
operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s
dual serial digital input buffers with 2 x 1 mux
integrated serial digital signal termination
built in reclocker
automatic or manual rate selection / indication (HD / SD)
SMPTE 292M and SMPTE 259M compliant de-scrambling
and NRZI - > NRZ decoding (with bypass)
de-scrambler bypass option
user selectable additional processing features including:
- CRC, TRS, ANC data checksum, line number and
EDH CRC error detection and correction
- programmable ANC data detection
- illegal code re-mapping
internal flywheel for noise immune H, V, F extraction
FIFO load Pulse
20-Bit / 10-Bit CMOS parallel output data bus
TTL compatible PCLK output
148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel digital output
automatic standards detection and indication
1.8V core power supply and 3.3V charge pump power
supply
3.3V digital I/O supply
JTAG test interface
small footprint compatible with GS1532
low power operation (typically < 375mW)
APPLICATIONS
APPLICATIONS
APPLICATIONS
APPLICATIONS
SMPTE 292M Serial Digital Interfaces
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
The GS1561 is a dual-rate reclocking deserializer,
compliant with SMPTE 292M and SMPTE 259M-C.
When used in conjunction with a GS1524 automatic cable
equalizer and a G01525 voltage controlled oscillator, a dual
rate (1.485 / 1.483Gb/s and 270Mb/s), receive solution can
be realized for HD-SDI, SD-SDI and DVB-ASI.
In addition to providing robust serial to parallel conversion
with word alignment, the GS1561 includes a range of
additional data processing functions such as error
detection and correction, automatic standards detection,
DVB-ASI and EDH support.
After reclocking and serial-to-parallel conversion, the
device performs NRZI to NRZ decoding, de-scrambling as
per SMPTE 292M / 259M and word alignment of the
incoming data stream. The SMPTE de-scrambler and word
alignment features can optionally be bypassed to support
the reception of signals with other coding schemes.
Two serial digital input buffers are provided with a 2x1
multiplexor. This allows the device to select from one of two
serial digital input signals.
The integrated reclocker features a very wide Input Jitter
Tolerance (IJT) of 0.3 UI, a rapid (typically less than
265s) asynchronous lock time, and full compliance with
DVB-ASI data streams.
The GS1561 also features a number of signal integrity
checks and measurement capabilities. Line-based CRC
errors, Line number errors, TRS errors, EDH CRC errors and
ancillary data check sum errors can all be detected. A
single 'error' pin is provided which is a logical 'or'ing of all
the detected errors. Individual error status can be read from
the host interface port.
In addition to detecting signal errors, the device also
includes the ability to correct all of the above detected
errors. Each error correction function may be individually
enabled / disabled via host interface control.
AVAILABLE PACKAGING
AVAILABLE PACKAGING
AVAILABLE PACKAGING
AVAILABLE PACKAGING
80-pin LQFP
GS1561
GS1561
GS1561
GS1561
+'/,1;
TM
,, Dual Rate Serial
Dual Rate Serial
Dual Rate Serial
Dual Rate Serial
Digital Reclocking Deserializer
Digital Reclocking Deserializer
Digital Reclocking Deserializer
Digital Reclocking Deserializer
22612 - 0
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GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
Copyright September 2001 Gennum Corporation. All rights reserved. Printed in Canada.
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Other processing functions include H:V:F timing extraction,
Y and C ancillary data indication and video standard
indication.
The device may also be used in data pass through mode
where no processing of the data is performed.
Parallel data outputs are provided in both 10 bit multiplexed
and 20 bit de-multiplexed format for HD and SD signal
rates. An associated parallel clock output signal is provided
operating at 148.5 or 148.5 / 1.001 MHz (HDTV 10 bit
multiplexed output), 74.25 or 74.25 / 1.001 MHz (HDTV 20
bit de-multiplexed output), 27 MHz (SD 10 bit multiplexed
and DVB-ASI output) and 13.5 MHz (SD 20 bit de-
multiplexed output).
The device will detect the presence of DVB-ASI sync words
and will automatically switch into bypass mode. The
DVB-ASI data will be word aligned to K28.5 sync characters
and 8b/10b decoding is applied to the received data
stream.
EDH FF and AP CRC calculation and comparison is
performed. Error flags are generated based on these CRC
comparisons. Re-calculated CRC's may be inserted into the
output data stream.
Line number generation is also performed by the device,
and for HDTV interfaces, the line number may be inserted
into the output data stream.
As well as detecting and extracting SMPTE 352M payload
identifier packets, the GS1561 can also automatically
identify the received video standard and the payload data
type. The detected video standard and data format may be
read via the host interface port.
GS1561 FUNCTIONAL BLOCK DIAGRAM
GS1561 FUNCTIONAL BLOCK DIAGRAM
GS1561 FUNCTIONAL BLOCK DIAGRAM
GS1561 FUNCTIONAL BLOCK DIAGRAM
SDI_1
SDI_1
SDI_2
SDI_2
RE-CLOCKER
S->P
SMPTE De-
scramble, Word
alignment and
flywheel
H V F
DOUT[19:0]
IP_SEL
CD1
CD2
carrier
detect
RESET_TEST
CORE_VCC
CORE_GND
ASI sync detect
CP_VCC
CP_GND
HOST INTERFACE / JTAG
TEST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
PD_VCC
PD_GND
DATA_ERROR
FIFO_LD
Y_ANC
C_ANC
POR
POWER ON
RESET
JTAG/HOST
IOPROC_EN/DIS
CRC check
Line mumber
check
TRS check
CSUM check
ANC data
detection
BUFF_VCC
K28.5 sync
detect, DVB-ASI
word alignment
and
8b/10b decode
CRC correct
Line number
correct
TRS correct
CSUM correct
EDH check &
correct
Illegal code re-
map
20bit/10bit
IO_VCC(x3)
IO_GND(x3)
I/O
Buffer
& mux
FW_EN/DIS
CP_CAP
DVB-ASI
pll lock
VCO
VCO
LB
LB_CONT
VCO_VCC
VCO_GND
MASTER_SLAVE
PCLK
LOCKED
LOCK DETECT
SMPTE_BYPASS
Smpte sync detect
GS1561 Dual Rate Serial Digital Re-clocking De-serializer
with DVB-ASI and EDH support.
REVISION NOTES:
Remove BGA package and Misc. updates and improvements.
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRODUCT BRIEF
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