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GS1535 HD-LINX IITM
Multi-Rate SDI
Automatic Reclocker
GS1535 Data Sheet
18557 - 8
February 2005
1 of 22
Key Features
SMPTE 292M, 259M and 344M compliant
Supports data rates of 143, 177, 270, 360, 540,
1483.5, 1485 Mb/s
Supports DVB-ASI at 270Mb/s
Auto and Manual Modes for rate selection
Standards indication in Auto Mode
4:1 input multiplexor
Lock Detect Output
On-chip Input and Output Termination
Differential inputs and outputs
Configuarble automatic Mute or Bypass when not
locked
Manual Bypass function
SD/HD indication output to control GS1528 Dual
Slew-Rate Cable Driver
Pb-free and Green
Single 3.3V power supply
Operating temperature range: 0C to 70C
Applications
SMPTE 292M, SMPTE 259M and SMPTE 344M
Serial Digital Interfaces
Description
The GS1535 Multi-Rate Serial Digital Reclocker is
designed to automatically recover the embedded clock
signal and re-time the data from a SMPTE 292M,
SMPTE 259M or SMPTE 344M compliant digital video
signal.
The device removes the high frequency jitter
components from the bit-serial stream. Input
termination is on-chip for seamless matching to 50
transmission lines. An LVPECL compliant output
interfaces seamlessly to the GS1528 Cable Driver
The GS1535 can operate in either auto or manual rate
selection mode. In Auto mode the GS1535
automatically detects and locks onto an incoming
SMPTE SDI data signal from 143 Mb/s to 1.485 Gb/s.
For single rate data systems, the GS1535 can be
configured to operate in manual mode. In both modes,
the GS1535 requires only one external crystal to set the
VCO frequency when not locked and provides
adjustment free operation. In systems which require
passing non-SMPTE data rates, the GS1535 will
automatically or manually enter a bypass mode in order
to pass the signal without reclocking.
The ASI/177 input pin allows for manual selection of
support of either 177Mb/s or DVB-ASI inputs.
GS1535 Functional Block Diagram
XTAL+ XTAL-
XTAL
OUT-
XTAL
OUT+
DDI_SEL[1:0]
DDI 1
DDI 2
DDI 3
DDI 0
LF+ LF-
KBB
DDO_MUTE
DDO/DDO
AUTOBYPASS
BYPASS
LD
AUTO/MAN
SS[2:0]
ASI/177
XTAL
OSC
BUFFER
DATA BUFFER
VCO
BYPASS
LOGIC
DIVIDE BY
2,4,6,8,12,16
PHASE
FREQUENCY
DETECTOR
DIVIDE BY
152, 160, 208
CONTROL LOGIC
CHARGE
PUMP
M
U
X
D
A
T
A
M
U
X
M
U
X
RE-TIMER
PHASE
DETECTOR
GS1535 Data Sheet
18557 - 8
February 2005
2 of 22
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................3
1.1 Pin Assignment ...............................................................................................3
1.2 Pin Descriptions ..............................................................................................4
2. Electrical Characteristics...........................................................................................7
2.1 Absolute Maximum Ratings ............................................................................7
2.2 DC Electrical Characteristics ..........................................................................7
2.3 AC Electrical Characteristics ...........................................................................8
2.4 Input/Output Circuits .....................................................................................10
3. Detailed Description ................................................................................................13
3.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................13
3.2 VCO ..............................................................................................................14
3.3 Charge Pump ................................................................................................14
3.4 Frequency Acquisition Loop --The Phase-Frequency Detector ...................14
3.5 Phase Acquisition Loop -- The Phase Detector ...........................................15
3.6 4:1 Input Mux ................................................................................................15
3.7 Automatic And Manual Data Rate Selection .................................................16
3.8 Bypass Mode ................................................................................................17
3.9 DVB/ASI Operation .......................................................................................17
3.10 LOCK ..........................................................................................................17
3.11 Output Drivers .............................................................................................18
3.12 Output Mute ................................................................................................18
4. Application Reference Design.................................................................................19
4.1 Typical Application Circuit .............................................................................19
5. References..............................................................................................................20
6. Package & Ordering Information.............................................................................20
6.1 Package Dimensions ....................................................................................20
6.2 Packaging Data .............................................................................................21
6.3 Ordering Information .....................................................................................21
7. Revision History ......................................................................................................22
GS1535 Data Sheet
18557 - 8
February 2005
3 of 22
1. Pin Out
1.1 Pin Assignment
P
XT
AL_OUT
-
XT
AL_OUT+
GND
VEE_DDO
VCC_DDO
DDO
DDO_VTT
GND
VCC_INT
VEE_INT
RSVD
RSVD
GND
GND
KBB
DDI_SEL0
DDI_SEL1
BYP
ASS
AUTOBYP
ASS
VCC_VCO
VEE_VCO
SS0
SS1
SS2
LD
RSVD
VCC_DIG
VEE_DIG
GND
DDI0
DDI0_VTT
GND
DDI1_VTT
GND
DDI1
DDI2_VTT
GND
DDI2
DDI3_VTT
GND
DDI3
GND
LF-
LF+
VCC_CP
VEE_CP
RSVD
RSVD
VCC
RSVD
VCC
GND
XT
AL-
XT
AL+
GS1535
64 PIN LQFP
TOP VIEW
DDI3
DDI2
DDI1
DDI0
AUTO/MAN
SD/HD
DDO_MUTE
RSVD
DDO
ASI/177
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
GS1535 Data Sheet
18557 - 8
February 2005
4 of 22
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Type
Description
1, 3
DDI0, DDI0
INPUT
Serial digital differential input 0.
2
DDI0_VTT
PASSIVE
Center tap of two 50
on-chip termination resistors between DDI0 and DDI0.
5, 7
DDI1,DDI1
INPUT
Serial digital differential input 1.
6
DDI1_VTT
PASSIVE
Center tap of two 50
on-chip termination resistors between DDI1 and DDI1.
9, 11
DDI2, DDI2
INPUT
Serial digital differential input 2.
10
DDI2_VTT
PASSIVE
Center tap of two 50
on-chip termination resistors between DDI2 and DDI2.
13, 15
DDI3, DDI3
INPUT
Serial digital differential input 3 .
14
DDI3_VTT
PASSIVE
Center tap of two 50
on-chip termination resistors between DDI3 and DDI3.
17, 18
DDI_SEL[1:0]
LOGIC INPUT
Serial digital input select.
19
BYPASS
LOGIC INPUT
Bypasses the reclocker stage (Active HIGH). When BYPASS is HIGH, it
overwrites the AUTOBYPASS setting.
20
AUTOBYPASS
LOGIC INPUT
Automatically bypasses the reclocker stage when the PLL is not locked
(Active HIGH).
21
AUTO/MAN
LOGIC INPUT
When active, the standard is automatically detected from the input data rate.
DDI_SEL1
DDI_SEL0
INPUT
SELECTED
0
0
DDI0
0
1
DDI1
1
0
DDI2
1
1
DDI3
GS1535 Data Sheet
18557 - 8
February 2005
5 of 22
24, 25, 26
SS[2:0]
BIDIRECTIONAL
When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to
which the PLL has locked.
When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a
selected data rate.
27
ASI/177
LOGIC INPUT
Disables 177Mbps data rate in the AUTO data rate detection circuit. This
prevents a FALSE LOCK to 177Mbps when using DVB/ASI.
28
LD
OUTPUT
LOCK DETECT. HIGH when the PLL is locked.
29
RSVD
RESERVED
DO NOT CONNECT.
33
SD/HD
OUTPUT
This signal is LOW when the reclocker has locked to 1.485Gbps or
1.485/1.001Gbps, and HIGH when the reclocker has locked to 143Mbps,
177Mbps, 270Mbps, 360Mbps, or 540Mbps.
34
KBB
ANALOG INPUT
Controls the loop bandwidth of the PLL. Leave this pin floating for serial
reclocking applications.
36
DDO_MUTE
LOGIC INPUT
Mutes the DDO/DDO outputs, when not in bypass mode.
44, 46
DDO, DDO
OUTPUT
Differential Serial Digital Outputs.
45
DDO_VTT
PASSIVE
Center tap of two 50
on-chip termination resistors between DDO and DDO..
50, 51
XTAL_OUT+,
XTAL_OUT-
OUTPUT
Differential buffered outputs of the reference oscillator.
52, 53
XTAL+, XTAL-
INPUT
Reference crystal input. Connect to the GO1535.
62, 63
LF+, LF-
PASSIVE
Loop filter capacitor connection. (C
LF
= 47nF).
4, 8, 12,16,
32, 35, 37,
43, 49, 54, 64
GND
PASSIVE
Recommended connect to GND.
43
GND_DRV
PASSIVE
Recommended connect to GND.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
Description
SS2
SS1
SS0
DATA RATE
SELECTED/FORCED (Mb/s)
0
0
0
143
0
0
1
177
0
1
0
270
0
1
1
360
1
0
0
540
1
0
1
1483.5/1485
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