GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: April 2002
Document No. 521 - 26 - 03
NO
T REC
O
MMEND
ED FOR NEW
D
ESIGNS
G
F
91
02A
DATA SHEET
FEATURES
FEATURES
FEATURES
FEATURES
improved performance over TMC2242 in applications
not requiring 1:1 low pass filtering
low power (60mA typical at = 20 MHz)
40 MHz maximum clock rate
single device exceeds CCIR 601 lowpass filter
requirements
true unity gain (0.0 dB) at DC
reduced output ringing with constant input in
interpolation mode
built-in TRS code protection
12 bit inputs and 16 bit outputs in 2's complement
signed or unsigned formats
user-selectable 8 to 16 bit output rounding
can also be operated as a 9 or 21 tap chroma
bandpass filter under user control
single +5 V power supply
three state outputs
APPLICATIONS
APPLICATIONS
APPLICATIONS
APPLICATIONS
CCIR 601-compliant oversampling video A/D and D/A
conversion
2:1 interpolation and decimation
4:2:2 to 4:4:4 format conversion
Chroma bandpass filtering
DEVICE DESCRIPTION
DEVICE DESCRIPTION
DEVICE DESCRIPTION
DEVICE DESCRIPTION
The GF9102A is a linear phase FIR digital filter that is
usable in a variety of video signal processing applications.
The device contains three separate fixed coefficient filters
and can be operated in three basic modes: 53 tap low pass
filter, 9 tap chroma bandpass filter or 21 tap chroma
bandpass filter.
In the 53 tap low pass filter mode, the GF9102A can
replace the TMC2242 in all applications, except those
requiring 1:1 low pass filtering, for improved performance
and full CCIR 601 compatibility. Specific improvements
include true unity gain at DC, 12.4 dB attenuation at s/4
with a single device, reduced output ringing with constant
input in interpolate mode, support for signed and unsigned
data formats, rounding to 10 and 8 bit CCIR 601 data
formats, masking of serial digital TRS codes in the data
stream, and elimination of the non-saturated-type overflow
condition. The device can be operated in both TMC2242
compatible modes and in GF9102A enhanced modes.
When used as a decimating post-filter with a double speed
oversampling analog-digital converter, the device greatly
reduces the cost and complexity of the associated analog
anti-aliasing pre-filter. In a similar fashion, when used as an
interpolating pre-filter with a double speed oversampling
digital-analog converter, the GF9102A simplifies the analog
reconstruction post-filter. The GF9102A also exceeds the
requirements for conversion between 4:2:2 and 4:4:4 signal
formats.
For chroma filtering applications, the GF9102A can be
operated as a 9 or 21 tap bandpass filter by selecting the
appropriate operating mode.
The GF9102A is packaged in a 44 pin PLCC and is pin
compatible with the TMC2242. The device operates with a
single +5 V supply.
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
ORDERING INFORMATION
ORDERING INFORMATION
ORDERING INFORMATION
PART NO.
PACKAGE
TEMPERATURE
GF9102ACPM
44 pin PLCC
0 C to 70 C
GF9102ACTM
44 pin PLCC Tape
0 C to 70 C
TIMING CONTROLS
OUTPUT FORMAT
TCO
RND
2..0
SYNC
INT
DEC
CLK
SO
3..0
DATA OUT
SO
15..0
OE
OUTPUT
PROCESSING
UNIT
M
U
X
BPF1
BPF2
53 TAP LPF
INPUT
PROCESSING
UNIT
DATA IN
SI
11..0
0XOWLGEN
TM
GF9102A
GF9102A
GF9102A
GF9102A
Decimating/Interpolating Digital Filter
Decimating/Interpolating Digital Filter
Decimating/Interpolating Digital Filter
Decimating/Interpolating Digital Filter
521 - 26 - 03
2
NO
T REC
O
MMEND
ED FOR NEW
D
ESIGNS
G
F
91
02A
PIN DESCRIPTION
PIN DESCRIPTION
PIN DESCRIPTION
PIN DESCRIPTION
SYMBOL
PIN NO.
TYPE
DESCRIPTION
CLK
42
I
System Clock.
TTL input. All timing specifications are referenced to the rising edge of clock.
SYNC
43
I
Data Synchronization. TTL input with internal pull-up. This input is used to synchronize the
incoming data with the GF9102A by holding SYNC high on clock N and low on clock N+1 when
the first data word is presented to the input SI
11..0
. SYNC may be held low until
resynchronization is desired, or it may be clocked at half the clock rate.
SI
11..0
40, 37, 36, 35,
34, 33, 32, 31,
30, 27, 26, 25
I
Input Data Port. TTL inputs with internal pull-downs. Data is presented to this registered 12-bit
data input port. This port can be programmed as two's complement signed or unsigned binary
format. See the following section on input data format. Data is latched internally on every clock
in decimate mode, and on every other clock in interpolate mode. SI
11
is the MSB.
TCO
2
I
Two's Complement Output Format Control. TTL input with internal pull-down. When TCO is high,
output data is presented in two's complement format. When TCO is low, the output is inverted
offset binary, obtained by inverting bits SO
14
through SO
0
, leaving SO
15
unchanged.
INT
44
I
Interpolate. Active low TTL input with internal pull-up. When the interpolate control is low, data is
input at full clock speed and the chip inserts zeros between samples, padding the input to
match the output rate. The GF9102A then interpolates between these alternate input data
points to achieve full output data rate.
DEC
1
I
Decimate. Active low TTL input with internal pull-down. When the decimate control is low, the
output register is driven at half system clock speed, decimating the output data stream. When
DEC and INT are low, the GF9102A will be programmed as a 21 tap or 9 tap bandpass filter
depending on the state of the SYNC input. See Operation Mode Control below for more detail.
RND
2..0
22, 23, 24
I
Output Rounding Control. TTL inputs with internal pull-down. These pins set the position of the
effective least significant bit of the output port by adding a rounding bit to the next lower
internal bit and zeroing all outputs below the rounding bit. Additional rounding functions are
added with the SO
1
control input. See Table 6.
SO
15..0
4, 5, 6, 7, 8, 9,
10, 11, 14, 15,
16, 17, 18, 19,
20, 21
O
Output Data Port. TTL outputs (SO
3..0
are bi-directional pins with an internal pull-down). The
filtered result is available at this registered 16-bit output port, half LSB rounded as determined
by the rounding control word RND
2..0
. SO
15
is the MSB. The SO
3..0
control inputs enable
additional formatting and rounding features as described below.
SO
3..0
18, 19, 20, 21
I/O
Output Data Port. TTL bi-directional pins with internal pull-down. The SO
0
control input enables
the unsigned input and output format. The SO
1
control input enables 8-bit rounding or CCIR
601 8-bit and 10-bit modes of operation. SO
3..2
are reserved for future functions.
OE
3
I
Output Enable. Active low TTL input with internal pull-up. When this asynchronous input is high,
the output data port is in the high impedance state.
V
DD
13, 29, 38
+5 V
5% power supply.
GND
12, 28, 39, 41
Ground
521 - 26 - 03
3
NO
T REC
O
MMEND
ED FOR NEW
D
ESIGNS
G
F
91
02A
Fig. 1 GF9102A Pin Connections
LOWPASS FILTER CHARACTERISTICS AT SAMPLING FREQUENCY OF 27 MH
LOWPASS FILTER CHARACTERISTICS AT SAMPLING FREQUENCY OF 27 MH
LOWPASS FILTER CHARACTERISTICS AT SAMPLING FREQUENCY OF 27 MH
LOWPASS FILTER CHARACTERISTICS AT SAMPLING FREQUENCY OF 27 MHz
PARAMETER
VALUE
Filter Order
53
Pass Band Ripple
<
0.02 dB
Pass Band Edge
5.75 MHz
DC Gain
0.00 dB
6.75 MHz (s/4) Attenuation
12.4 dB
Minimum Stop Band Attenuation
> 58 dB
Stop Band Edge
7.4 MHz
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
GF9102A
Top View
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
SO
13
SO
14
SO
15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
SO
3
SO
2
SO
1
SO
0
RND
2
RND
1
RND
0
SI
0
SI
1
SI
2
GND
521 - 26 - 03
4
NO
T REC
O
MMEND
ED FOR NEW
D
ESIGNS
G
F
91
02A
Fig. 2 Frequency Response of the Decimation/Interpolation Filter
(Sampling at 27 MHz)
Fig. 4 Step Response of Decimation Filter
Fig. 6 Frequency Response of the Bandpass Filter Transition Band
(Sampling at 14.31818 MHz)
Fig. 3 Frequency Response of the Decimation/Interpolation Filter
Passband (Sampling at 27 MHz)
Fig. 5 Frequency Response of the Bandpass Filter (Sampling at
14.31818 MHz)
Fig. 7 Frequency Response of the Bandpass Filter Passband
(Sampling at 14.31818 MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
0 2 4 6 8 10 12 14
FREQUENCY (MHz)
MAGNITUDE (dB)
CCIR601
GF9102A
110
100
90
80
70
60
50
40
30
20
10
0
-10
0 10 20 30 40 50 60 70 80
SAMPLE NUMBER
% FULL SCALE
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
6
5
4
3
2
1
0
-1
-2
-3
-4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
FREQUENCY (MHz)
MAGNITUDE (dB) 21 T
AP BPF
MAGNITUDE (dB) 9 T
AP BPF
21 TAP BPF
9 TAP BPF
0.05
0.0375
0.025
0.0125
0
-0.0125
-0.025
-0.0375
-0.05
0 1 2 3 4 5 6
FREQUENCY (MHz)
MAGNITUDE (dB)
CCIR601
GF9102A
0
-20
-40
-60
-80
-100
6
-15
-36
-58
-79
-100
0 1 2 3 4 5 6 7
FREQUENCY (MHz)
MAGNITUDE (dB) 21 T
AP BPF
MAGNITUDE (dB) 9 T
AP BPF
21 TAP BPF
9 TAP BPF
0
-0.005
-0.01
-0.015
-0.02
6.02
6.015
6.01
6.005
6.00
2.579545 3.079545 3.579545 4.079545 4.579545
FREQUENCY (MHz)
MAGNITUDE (dB) 21 T
AP BPF
MAGNITUDE (dB) 9 T
AP BPF
21 TAP BPF
9 TAP BPF
521 - 26 - 03
5
NO
T REC
O
MMEND
ED FOR NEW
D
ESIGNS
G
F
91
02A
TABLE 1: INPUT DATA FORMAT AND BIT WEIGHTING
TABLE 1: INPUT DATA FORMAT AND BIT WEIGHTING
TABLE 1: INPUT DATA FORMAT AND BIT WEIGHTING
TABLE 1: INPUT DATA FORMAT AND BIT WEIGHTING
Two's complement signed binary, data range: -1
SI < 1
SI
11
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
SI
2
SI
1
SI
0
-2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
Unsigned binary, data range: 0
SI < 256
SI
11
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
SI
2
SI
1
SI
0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
TABLE 2: OUTPUT DATA FORMAT AND BIT WEIGHTING
TABLE 2: OUTPUT DATA FORMAT AND BIT WEIGHTING
TABLE 2: OUTPUT DATA FORMAT AND BIT WEIGHTING
TABLE 2: OUTPUT DATA FORMAT AND BIT WEIGHTING
Two's complement signed binary, data range: -1
SI < 1
SO
15
SO
14
SO
13
SO
12
SO
11
SO
10
SO
9
SO
8
SO
7
SO
6
SO
5
SO
4
SO
3
SO
2
SO
1
SO
0
-2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
2
-9
2
-10
2
-11
2
-12
2
-13
2
-14
2
-15
Unsigned binary, data range: 0
SI < 256
SO
15
SO
14
SO
13
SO
12
SO
11
SO
10
SO
9
SO
8
SO
7
SO
6
SO
5
SO
4
SO
3
SO
2
SO
1
SO
0
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
TABLE 3: OPERATION MODE CONTROL
TABLE 3: OPERATION MODE CONTROL
TABLE 3: OPERATION MODE CONTROL
TABLE 3: OPERATION MODE CONTROL
DEC
INT
SNYC
MODE
DESCRIPTION
DEVICE LATENCY
NOTES
0
0
0
Bandpass 1
21 Tap Bandpass
18 Clock Cycles
2
0
0
1
Bandpass 2
9 Tap Bandpass Gain=2
18 Clock Cycles
2
0
1
Sync
Decimating
Gain=1
33 Clock Cycles
1
1
0
Sync
Interpolating
Gain=0.5
33 Clock Cycles
1
1
0
Sync
Interpolating
Gain=1 for unsigned input
3
33 Clock Cycles
2
1
1
Sync
Interpolating
Top 12 bit pass through
33 Clock Cycles
2
NOTES
1. This operating mode is compatible with TMC2242.
2. This is an enhanced operating mode of the GF9102A
3. This mode is invoked using the SO
0
pin. See I/O Format Control below.
PDF 
ZIP