DS04-21371-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Fractional-N
PLL Frequency
Synthesizer
MB15F83UL
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DESCRIPTION
The Fujitsu MB15F83UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.
The Fractional-N PLL operating up to 2000 MHz and the integer PLL operating up to 600 MHz are integrated on
one chip.
The MB15F83UL is used, as charge pump which is well-balanced output current with 1.5 mA and 6 mA selectable
by serial data, direct power save control and digital lock detector. In addition, the MB15F83UL adopts a new
architecture to achieve fast lock.
The new package (Thin Bump Chip Carrier20) decreases a mount area of MB15F83UL more than 30
%
comparing
with the former B.C.C.16 (for dual PLL, MB15F03SL) .
The MB15F83UL is ideally suited for wireless mobile communications, such as GSM.
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FEATURES
High frequency operation
: RF synthesizer : 2000 MHz Max.
: IF synthesizer : 600 MHz Max.
Low power supply voltage
: V
CC
=
2.7 V to 3.6 V
Ultra Low power supply current
: I
CC
=
5.8 mA Typ. (V
CC
=
Vp
=
3.0 V, Ta
=
+
25
C, SW
=
0 in IF and RF locking
state)
(Continued)
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PACKAGES
20-pin, Plastic TSSOP
20-pad, Plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)
MB15F83UL
2
(Continued)
Direct power saving function : Power supply current in power saving mode
Typ. 0.1
A (V
CC
=
Vp
=
3.0 V, Ta
=
+
25
C) , Max. 10
A (V
CC
=
Vp
=
3.0 V)
Fractional function : modulo 13 fixed (implemented in RF-PLL)
Dual modulus prescaler : 2000 MHz prescaler (16/17 fixed) /600 MHz prescaler (8/9 or 16/17)
Serial input programmable reference divider : RF : 7 bit (3 to 127) /IF : 14 bit (3 to 16383)
Serial input programmable divider consisting of :
RF section - Binary 4-bit swallow counter : 0 to 15
- Binary 10-bit programmable counter : 18 to 1,023
- Binary 4-bit fractional counter numerator : 0 to 15
IF section - Binary 4-bit swallow counter : 0 to 15
- Binary 11-bit programmable counter : 3 to 2,047
On-chip phase comparator for fast lock and low noise
Operating temperature : Ta
=
-
40
C to
+
85
C
Small package Bump Chip Carrier.0 (3.4 mm
3.6 mm
0.6 mm)
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PIN ASSIGNMENTS
(BCC-20)
TOP VIEW
(LCC-20P-M05)
GND
Clock
D
OIF
1
2
3
4
5
6
7
8
9 10 11
12
13
14
15
16
19 18 17
20
GND
IF
GND
RF
V
CCIF
Vp
IF
LE
fin
RF
fin
IF
V
CCRF
PS
RF
PS
IF
Xfin
RF
Xfin
IF
OSC
IN
Data
LD/fout
D
ORF
Vp
RF
(TSSOP-20)
TOP VIEW
(FPT-20P-M06)
OSC
IN
GND
fin
IF
Xfin
IF
GND
IF
V
CCIF
PS
IF
Vp
IF
D
OIF
LD/fout
Clock
Data
LE
fin
RF
Xfin
RF
GND
RF
V
CCRF
PS
RF
Vp
RF
D
ORF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MB15F83UL
3
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PIN DESCRIPTION
Pin no.
Pin
name
I/O
Descriptions
TSSOP
BCC
1
19
OSC
IN
I
The programmable reference divider input pin. TCXO should be connected with
an AC coupling capacitor.
2
20
GND
Ground pin for OSC input buffer and the shift register circuit.
3
1
fin
IF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
4
2
Xfin
IF
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3
GND
IF
Ground pin for the IF-PLL section.
6
4
V
CCIF
Power supply voltage input pin for the IF-PLL section (except for the charge
pump circuit) , the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
7
5
PS
IF
I
Power saving mode control signal pin for the IF-PLL section. This pin must be set
at "L" when the power supply is started up. (Open is prohibited.)
PS
IF
=
"H"; Normal mode / PS
IF
=
"L"; Power saving mode
8
6
Vp
IF
Power supply voltage input pin for the IF-PLL charge pump.
9
7
Do
IF
O
Charge pump output pin for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
8
LD/fout O
Look detect signal output (LD) /phase comparator monitoring output (fout) pins.
The output signal is selected by an LDS bit in a serial data.
LDS bit
=
"H"; outputs fout signal / LDS bit
=
"L"; outputs LD signal
11
9
Do
RF
O
Charge pump output pin for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
12
10
Vp
RF
Power supply voltage input pin for the RF-PLL charge pump.
13
11
PS
RF
I
Power saving mode control pin for the RF-PLL section. This pin must be set at
"L" when the power supply is started up. (Open is prohibited. )
PS
RF
=
"H"; Normal mode / PS
RF
=
"L"; Power saving mode
14
12
V
CCRF
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit) .
15
13
GND
RF
Ground pin for the RF-PLL section.
16
14
Xfin
RF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
fin
RF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be AC coupling.
18
16
LE
I
Load enable signal input pin (with the schmitt trigger circuit.)
On a rising edge of load enable, data in the shift register is transferred to the cor-
responding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input pin (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
MB15F83UL
4
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BLOCK DIAGRAM
7
3
4
1
17
11
10
16
13
18
19
20
12
15
14
2
9
8
5
6
PS
IF
fin
IF
Xfin
IF
OSC
IN
(5)
(7)
(8)
(9)
(18)
(17)
(16)
(11)
(14)
(15)
(1)
(2)
(19)
Power
saving
IF-PLL
Prescaler
(IF-PLL)
8/9, 16/17
4-bit latch
11-bit latch
Binary 14-bit pro-
grammable ref.
counter (IF-PLL)
Binary 11-bit
programmable
counter
(IF-PLL)
VCC
IF
GND
IF
Vp
IF
(4)
(3)
(6)
(10)
(13)
(12)
(20)
fp
IF
Phase
comp.
(IF-PLL)
Charge
pump
(IF-PLL)
Do
IF
LD/fout
14-bit latch
Binary 4-bit
swallow counter
(IF-PLL)
LDS
T1
T2
SWC
FCC
CSC
6-bit latch
Lock
Det.
(IF-PLL)
LD
IF
Slector
LD
IF
LD
RF
fr
IF
fr
RF
fp
IF
fp
RF
OR
Lock
Det.
(RF-PLL)
Phase
comp.
(RF-PLL)
Charge
pump
(RF-PLL)
Do
RF
SC
(RF-PLL)
SC1
SC2
Vp
RF
GND
RF
GND
Vcc
RF
Clock
Data
LE
PS
RF
Xfin
RF
fin
RF
Schmitt
circuit
Schmitt
circuit
Schmitt
circuit
C
N
1
C
N
2
C
N
3
23-bit shift
register
Latch selector
Power
saving
RF-PLL
Prescaler
(RF-PLL)
16/17
MD2
Binary 4-bit
swallow counter
(RF-PLL)
Binary 10-bit
programmable
counter
(RF-PLL)
4-bit latch
10-bit latch
MD1
F
1
F
2
F
3
F
4
4-bit latch
Fractional
Counter
13
fr
RF
fp
RF
fr
RF
fp
RF
Selector
SC1
SC2
SFW
FCF
CSF
5-bit latch
7-bit latch
Binary 7-bit pro-
grammable ref.
counter
(RF-PLL)
OR
O : TSSOP 20
( ) : BCC 20
MB15F83UL
5
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ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter
Symbol
Rating
Unit
Min.
Max.
Power supply voltage
V
CC
-
0.5
+
4.0
V
Vp
V
CC
+
4.0
V
Input voltage
V
I
-
0.5
V
CC
+
0.5
V
Output voltage
LD / fout
V
O
GND
V
CC
V
Do
V
DO
GND
Vp
V
Storage temperature
Tstg
-
55
+
125
C
Parameter
Symbol
Value
Unit
Remark
Min.
Typ.
Max.
Power supply voltage
V
CC
2.7
3.0
3.6
V
V
CCRF
=
V
CCIF
Vp
V
CC
3.0
3.6
V
Input voltage
V
I
GND
V
CC
V
Operating temperature
Ta
-
40
+
85
C
MB15F83UL
6
*
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ELECTRICAL CHARACTERISTICS
(V
CC
=
2.7 V to 3.6 V, Ta
=
-
40
C to
+
85
C)
(Continued)
Parameter
Symbol
Condition
Value
Unit
Min.
Typ.
Max.
Power supply current
I
CCIF
*1
fin
IF
=
480 MHz, SW
C
=
0
V
CCIF
=
Vp
IF
=
3.0 V
1.0
1.6
2.3
mA
I
CCRF
*1
fin
RF
=
2000 MHz
V
CCRF
=
Vp
RF
=
3.0 V
2.8
4.2
5.8
mA
Power saving current
I
PSIF
PS
=
"L"
0.1
*2
10
A
I
PSRF
PS
=
"L"
0.1
*2
10
A
Operating frequency
fin
IF
*3
fin
IF
IF PLL
100
600
MHz
fin
RF
*3
fin
RF
RF PLL
400
2000
MHz
OSC
IN
f
OSC
3
40
MHz
Input sensitivity
fin
IF
Pfin
IF
IF PLL, 50
system
-
15
+
2
dBm
fin
RF
Pfin
RF
RF PLL, 50
system
-
15
+
2
dBm
OSC
IN
V
OSC
0.5
V
CC
Vp-p
"H" level input voltage
Data,
Clock,
LE
V
IH
Schmitt triger input
0.7 V
CC
+
0.4
V
"L" level input voltage
V
IL
Schmitt triger input
0.3 V
CC
-
0.4
"H" level input voltage
PS
IF
PS
RF
V
IH
0.7 V
CC
V
"L" level input voltage
V
IL
0.3 V
CC
"H" level input current
Data,
Clock,
LE,
PS
IF
,
PS
RF
I
IH
*4
-
1.0
+
1.0
A
"L" level input current
I
IL
*4
-
1.0
+
1.0
"H" level input current
OSC
IN
I
IH
0
+
100
A
"L" level input current
I
IL
*4
-
100
0
"H" level output voltage LD/
fout
V
OH
V
CC
=
Vp
=
3.0 V, I
OH
=
-
1 mA
V
CC
-
0.4
V
"L" level output voltage
V
OL
V
CC
=
Vp
=
3.0 V, I
OL
=
1 mA
0.4
"H" level output voltage Do
IF
Do
RF
V
DOH
V
CC
=
Vp
=
3.0 V, I
DOH
=
-
0.5 mA Vp
-
0.4
V
"L" level output voltage
V
DOL
V
CC
=
Vp
=
3.0 V, I
DOL
=
0.5 mA
0.4
High impedance
cutoff current
Do
IF
Do
RF
I
OFF
V
CC
=
Vp
=
3.0 V
V
OFF
=
0.5 V to Vp
-
0.5 V
2.5
nA
"H" level output current LD/
fout
I
OH
*4
V
CC
=
Vp
=
3.0 V
-
1.0
mA
"L" level output current
I
OL
V
CC
=
Vp
=
3.0 V
1.0
MB15F83UL
7
(Continued)
(V
CC
=
2.7 V to 3.6 V, Ta
=
-
40
C to
+
85
C)
*1 : Conditions ; fosc
=
13 MHz, Ta
=
+
25
C in locking state.
*2 : V
CCIF
=
Vp
IF
=
V
CCRF
=
Vp
RF
=
3.0 V, fosc
=
13 MHz, Ta
=
+
25
C, in power saving mode.
*3 : AC coupling. 1000 pF capacitor is connected.
*4 : The symbol "" (minus) means direction of current flow.
*5 : V
CC
=
Vp
=
3.0 V, Ta
=
+
25
C (||I
3
|
-
|I
4
||)
/
[ (|I
3
|
+
|I
4
|)
/
2]
100 (
%
)
*6 : V
CC
=
Vp
=
3.0 V, Ta
=
+
25
C [ (||I
2
|
-
|I
1
||)
/
2]
/
[ (|I
1
|
+
|I
2
|)
/
2]
100 (
%
) (Applied to each l
DOL
and l
DOH
)
*7 : V
CC
=
Vp
=
3.0 V, Ta
=
+
25
C[ (||I
DO (85
C)
|
-
|I
DO (40
C)
||)
/
2]
/
[ (|I
DO (85
C)
|
+
|I
DO (40
C)
|)
/
2]
100 (
%
) (Applied
to each I
DOL
and I
DOH
)
Parameter
Symbol
Condition
Value
Unit
Min.
Typ.
Max.
"H" level output
current
Do
IF
Do
RF
I
DOH
*4
V
CC
=
Vp
=
3.0 V
V
DOH
=
Vp
/
2
Ta
=
+
25
C
CS bit
=
"H"
-
8.2
-
6.0
-
4.1
mA
CS bit
=
"L"
-
2.2
-
1.5
-
0.8
mA
"L" level output
current
I
DOL
V
CC
=
Vp
=
3.0 V
V
DOL
=
Vp
/
2
Ta
=
+
25
C
CS bit
=
"H"
4.1
6.0
8.2
mA
CS bit
=
"L"
0.8
1.5
2.2
mA
Charge pump
current rate
I
DOL
/I
DOH
I
DOMT
*5
V
DO
=
Vp
/
2
3
%
vs V
DO
I
DOVD
*6
0.5 V
V
DO
Vp
-
0.5 V
10
%
vs Ta
I
DOTA
*7
-
40
C
Ta
+
85
C,
V
DO
=
Vp
/
2
5
%
I
DOL
I
1
I
3
I
2
I
1
I
4
I
2
0.5
Vp/2
Vp
-
0.5
Vp
I
DOH
output voltage (V)
MB15F83UL
8
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FUNCTIONAL DESCRIPTION
1.
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections and programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary code is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
Note : (CN3
=
1 is pohibited)
(1) Serial data format
The programmable
reference counter for
the IF-PLL
The programmable
counter and the
swallow counter for the
IF-PLL
The programmable
reference counter for
the RF-PLL
The prgrammable
counter and the
swallow counter for
the RF-PLL
CN1
0
1
0
1
CN2
0
0
1
1
CN3
0
0
0
0
Note: Data input with MSB first.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
0
0
R
C1
R
C2
R
C3
R
C4
R
C5
R
C6
R
C7
R
C8
R
C9
R
C10
R
C11
R
C12
R
C13
R
C14
LDS
T1
T2 SW
C
FC
C
CS
C
1
0
0
A
C1
A
C2
A
C3
A
C4
0
0
0
N
C1
N
C2
N
C3
N
C4
N
C5
N
C6
N
C7
N
C8
N
C9
N
C10
N
C11
X
X
0
1
0
R
F1
R
F2
R
F3
R
F4
R
F5
R
F6
R
F7
0
0
0
0
0
0
0
0 SC1 SC2
1
FC
F
CS
F
1
1
0
A
F1
A
F2
A
F3
A
F4
0
N
F1
N
F2
N
F3
N
F4
N
F5
N
F6
N
F7
N
F8
N
F9
N
F10
F1
F2
F3
F4
0
R
C1
to R
C14
: Divide ratio setting bits for the reference counter of the IF (3 to 16383)
A
C1
to A
C4
: Divide ratio setting bits for the swallow counter of the IF (0 to 15, A < N)
N
C1
to N
C11
: Divide ratio setting bits for the programmable counter of the IF (3 to 2047)
LDS, T1, T2
: Select bits for the lock detect output or a monitoring phase comparison frequency
SW
C
: Divide ratio setting for the prescaler of the IF
FC
C
: Phase control bit for the phase detector of the IF
CS
C
: Charge pump current select bit of the IF
R
F1
to R
F7
: Divide ratio setting bits for the reference counter of the RF (3 to 127)
A
F1
to A
F4
: Divide ratio setting bits for the swallow counter of the RF (0 to 15, A < N
-
2)
N
F1
to N
F10
: Divide ratio setting bits for the programmable counter of the RF (18 to 1023)
F1 to F4
: Fractional-N increment setting bit for the fractional accumulator (0 to 15, F < Q)
SC1, SC2
: Spurious cancel set bit of the RF.
FC
F
: Phase control bit for the phase detector of the RF.
CS
F
: Charge pump current select bit of the RF
X
: Dummy bit (Set "0" or "1")
LSB
MSB
Direction of data shift
Control bit (CN3)
Control bit (CN2)
Control bit (CN1)
MB15F83UL
9
(2) Data Setting
RF synthesizer Data Setting (Fractional-N)
The divide ratio can be calculated using the following equation :
f
VCORF
=
N
TOTAL
fosc
R
N
TOTAL
=
P
N
+
A
+
F
/
Q
(A < N
-
2, F < Q)
Binary 7
-
bit Programmable Reference Counter Data Setting
(R
F1
to R
F7
)
Note : Divide ratio less than 3 is prohibited.
Fractional-N incremant of the fractional accumulator Data Setting
(
F1
to
F4
)
Note : F < Q
f
VCORF
: Output frequency of external voltage controlled oscillator (VCO)
N
TOTAL
: Total division ratio from prescaler input to the phase detector input
fosc
: Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 7 bit reference counter (3 to 127)
P
: Preset divide ratio of modulus prescaler (16 fixed)
N
: Preset divide ratio of binary 10 bit programmable counter (18 to 1023)
A
: Preset divide ratio of binary 4 bit swallow counter (0 to 15)
F
: A numerator of fractional-N (0 to 15)
Q
: A denominator of fractional-N, modulo 13
Divide ratio (R)
R
F7
R
F6
R
F5
R
F4
R
F3
R
F2
R
F1
3
0
0
0
0
0
1
1
4
0
0
0
0
1
0
0
52
0
1
1
0
1
0
0
127
1
1
1
1
1
1
1
Setting value(F)
F4
F3
F2
F1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
15
1
1
1
1
MB15F83UL
10
Binary 10
-
bit Programable Counter Data Setting
(
N
F1
to
N
F10
)
Note : Divide ratio less than 18 is prohibited.
Binary 4-bit Swallow Counter Data Setting (A
F1
to A
F4
)
Note : A < N
-
2
Spurious cancel Bit Setting
Note : The bits set how much the amount of spurious cancel.
If the Large is selected, a spurious is tended to become small.
Phase Comparator Phase Switching Data Setting
Notes :
Z
=
High-Z
Depending upon the VCO and LPF polarity, FC bit should be set.
Charge pump current select Bit Setting
Divide ratio (N)
N
F10
N
F9
N
F8
N
F7
N
F6
N
F5
N
F4
N
F3
N
F2
N
F1
18
0
0
0
0
0
1
0
0
1
0
19
0
0
0
0
0
1
0
0
1
1
32
0
0
0
0
1
0
0
0
0
0
1023
1
1
1
1
1
1
1
1
1
1
Divide ratio (A)
A
F4
A
F3
A
F2
A
F1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
15
1
1
1
1
Spurious cancel amount
SC1
SC2
Large
0
0
Midium
0
1
Small
1
0
FC
F
=
=
=
=
High
FC
F
=
=
=
=
Low
D
O
D
O
fr
>
fp
H
L
fr
=
fp
Z
Z
fr < fp
L
H
VCO polarity
1
2
CS
F
Current value
1
6.0 mA
0
1.5 mA
MB15F83UL
11
IF synthesizer Data Setting (Integer)
The divide ratio can be calculated using the following equation :
f
VCOIF
=
[ (P
N)
+
A]
fosc
R
(A < N)
Binary 14-bit Programmable Reference Counter Data Setting (R
C1
to R
C14
)
Note : Divide ratio less than 3 is prohibited.
Binary 11-bit Programmable Counter Data Setting (N
C1
to N
C11
)
Note : Divide ratio less than 3 is prohibited.
Binary 4-bit Swallow Counter Data Setting (A
C1
to A
C4
)
Note : A < N
Prescaler Data Setting (SW
C
)
Divide ratio
(R)
R
C14
R
C13
R
C12
R
C11
R
C10
R
C9
R
C8
R
C7
R
C6
R
C5
R
C4
R
C3
R
C2
R
C1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide ratio (N) N
C11
N
C10
N
C9
N
C8
N
C7
N
C6
N
C5
N
C4
N
C3
N
C2
N
C1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
2047
1
1
1
1
1
1
1
1
1
1
1
Divide ratio (A)
A
C4
A
C3
A
C2
A
C1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
15
1
1
1
1
SW
C
Prescaler divide ratio
1
8/9
0
16/17
f
VCOIF
: Output frequency of external voltage controlled oscillator (VCO)
P
: Preset divide ratio of modulus prescaler (8 or 16)
N
: Preset divide ratio of binary 11 bit programmable counter (3 to 2047)
A
: Preset divide ratio of binary 4 bit swallow counter (0 to 15)
fosc
: Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14 bit reference counter (3 to 16383)
MB15F83UL
12
Phase Comparator Phase Switching Data Setting
Notes :
Z
=
High-Z
Depending upon the VCO and LPF polarity, FC bit should be set.
Charge pump current select Data Setting (CS
C
)
Common setting
LD/fout Output Select Data Setting
FC bit Setting
When designing a synthesizer, the FC bit setting depends on the VCO and LPF characteristics.
FC
C
=
=
=
=
High
FC
C
=
=
=
=
Low
D
O
D
O
fr
>
fp
H
L
fr
=
fp
Z
Z
fr < fp
L
H
CS
C
Do current
1
6.0 mA
0
1.5 mA
LD/fout
LDS
T1
T2
LD output
0
fout
output
fr
IF
1
0
0
fr
RF
1
1
0
fp
IF
1
0
1
fp
RF
1
1
1
(1)
(2)
High
Max.
When the LPF and VCO characteristics are similar to (1) ,
set FC bit "H".
When the VCO characteristics are similar to (2) ,
set FC bit "L".
VCO output
frequency
LPF output voltage
MB15F83UL
13
2.
Power Saving Mode (Intermittent Mode Control)
PS Pin Setting
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters the power saving mode, reducing the current consumption.
See "
s
ELECTRICAL CHARACTERISTICS" for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is shown in "
s
PHASE DETECTOR OUTPUT WAVEFORM the LD Output
Logic table.
Setting the PS pin high releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes:
When power (V
CC
) is first applied, the device must be in standby mode and PS
=
Low, for at least 1
s.
PS pin must be set "L" for Power ON.
PS pin
Status
H
Normal mode
L
Power saving mode
ON
OFF
V
CC
Clock
Data
LE
PS
(1)
(2)
(3)
t
V
1
s
t
PS
100 ns
(1) PS
=
L (power saving mode) at Power ON
(2) Set serial data 1
s after power supply remains stable (V
CC
2.2 V) .
(3) Release power saving mode (PS : L
H) 100 ns after setting serial data.
MB15F83UL
14
3.
Serial Data Input Timing
LSB
MSB
Clock
Data
LE
t
7
t
1
t
2
t
3
t
4
t
5
t
6
1st data
2nd data
Control bit
Invalid data
On the rising edge of the clock, one bit of data is transferred into shift register.
Note : LE should be "L" when the data is transferred into the shift register.
Parameter
Min.
Typ.
Max.
Unit
Parameter
Min.
Typ.
Max.
Unit
t
1
20
ns
t
5
100
ns
t
2
20
ns
t
6
20
ns
t
3
30
ns
t
7
100
ns
t
4
30
ns
MB15F83UL
15
s
s
s
s
PHASE DETECTOR OUTPUT WAVEFORM
LD Output Logic Table
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
fr
IF/RF
fp
IF/RF
LD
D
OIF/RF
t
WU
t
WL
D
OIF/RF
(FC bit = High)
(FC bit = Low)
Z
H
L
Z
H
L
Notes:
Phase error detection range
=
-
2
to
+
2
Pulses on Do
IF/RF
signals are output to prevent dead zone.
LD output becomes low when phase error is t
WU
or more.
LD output becomes high when phase error is t
WL
or less and continues to be so for three cycles or more.
t
WU
and t
WL
depend on OSC
IN
input frequency as follows.
t
WU
2/fosc
[
s
]
: i.e. t
WU
153.8 ns when fosc
=
13.0 MHz
t
WU
4/fosc
[
s
]
: i.e. t
WL
307.7 ns when fosc
=
13.0 MHz
MB15F83UL
16
s
s
s
s
TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC
IN
)
MB15F83UL
S.G
P.G
S.G
fout
Oscilloscope
1000 pF
50
Vp
IF
V
CCIF
0.1
F
0.1
F
1000 pF
1000 pF
50
LD/fout
D
ORF
Vp
RF
PS
RF
V
CCRF
GND
RF
Xfin
RF
fin
RF
LE
Data Clock
D
OIF
Vp
IF
PS
IF
V
CCIF
GND
IF
Xfin
IF
fin
IF
GND OSC
IN
Controller (divide
ratio setting)
1000 pF
50
1000 pF
Vp
RF
V
CCRF
0.1
F
0.1
F
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
Note : TSSOP-20
MB15F83UL
17
s
s
s
s
TYPICAL CHARACTERISTICS
1.
fin input sensitivity
RF-PLL input sensitivity vs. Input frequency
fin
RF
(MHz)
Pfin
RF
(dBm)
IF-PLL input sensitivity vs. Input frequency
fin
IF
(MHz)
Pfin
IF
(dBm)
SPEC
0
500
1000
1500
2000
2500
10
0
-
10
-
20
-
30
-
40
-
50
2.7 V
3.0 V
3.6 V
SPEC
3.3 V
Ta
=
+
25
C
SPEC
0
500
1000
1500
2000
10
0
-
10
-
20
-
30
-
40
-
50
2.7 V
3.0 V
3.3 V
3.6 V
Ta
=
+
25
C
MB15F83UL
18
2.
OSC
IN
input sensitivity
0
50
100
150
200
250
300
10
0
-
10
-
20
-
30
-
40
-
50
-
60
V
CC
=
2.7 V
V
CC
=
3.0 V
V
CC
=
3.6 V
SPEC
Ta
=
+
25
C
SPEC
Input sensitivity vs. Input frequency
Input frequency f
OSC
(MHz)
Input sensitivity V
OSC
(dBm)
MB15F83UL
19
3.
RF-PLL Do output current
20
-
20
0
0
1
2
3
1.5 mA mode
6.0 mA mode
20
-
20
0
0
1
2
3
Charge pump output current I
DO
(mA)
I
DO
-
V
DO
Charge pump output voltage V
DO
(V)
I
DO
-
V
DO
Charge pump output current I
DO
(mA)
Charge pump output voltage V
DO
(V)
MB15F83UL
20
4.
IF-PLL Do output current
1.5 mA mode
6.0 mA mode
I
DO
-
V
DO
Charge pump
output current I
DO
(mA)
Charge pump
output voltage V
DO
(V)
I
DO
-
V
DO
Charge pump
output current I
DO
(mA)
Charge pump
output voltage V
DO
(V)
10.0
-
10.0
V
CC
=
Vp
=
2.7 V
0
0.0
1.0
2.0
3.0
V
CC
=
Vp
=
2.7 V
10.0
0
-
10.0
0.0
1.0
2.0
3.0
MB15F83UL
21
5.
fin input impedance
45.859
-
188.77
1 GHz
25.48
-
103.67
1.7 GHz
22.152
-
83.391
2 GHz
1
:
2
:
3
:
START 1 000.000 000 MHz
STOP 2 600.000 000 MHz
1.1765 pF
1
3
2
325.78
-
732.22
100 MHz
21.516
-
170.72
500 MHz
12.422
-
108.38
750 MHz
1
:
2
:
3
:
START .030 000 MHz
STOP 1 000.000 000 MHz
4
:
9.3437
-
75.625
2.1045 pF
1 000.000 000 MHz
1
3
2
4
fin
R
input impedance
fin
IF
input impedance
MB15F83UL
22
6.
OSC
IN
input impedance
28.625
-
667.75
100 MHz
2.1273 k
-
5.9445 k
10 MHz
2.1273 k
-
5.9445 k
10 MHz
1
:
2
:
3
:
START .030 000 MHz
STOP 100.000 000 MHz
4
:
092.56
-1.3177 k
2.4157 pF
50.000 000 MHz
1
3
2
4
3
OSC
IN
input impedance
MB15F83UL
23
s
s
s
s
REFERENCE INFORMATION
(
for Lock
-
up Time
,
Phase Noise and Reference Leakage
)
S.G.
OSC
IN
fin
VCO
D
O
LPF
Test Circuit
Spectrum
Analyzer
3.0 k
3900 pF
10 k
390 pF
82 pF
f
VCO
=
1733 MHz
V
CC
=
3.0 V
K
V
=
44 MHz/V
V
VCO
=
3.5 V
fr
=
200 kHz
Ta
=
+
25
C
f
OSC
=
13 MHz
CP : 6 mA mode
LPF
QM
=
13
PLL Reference Leakage
PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
CENTER 1.733000 GHz
RBW 10 kHz
VBW 10 kHz
SPAN 1.000 MHz
SWP 50.0 ms
MKR
-
69.00 dB
200 kHz
VAVG 100
10 dB/
MKR
200 kHz
-
69.00 dB
D
ATTEN 10 dB
RL 0 dBm
CENTER 1.73299933 GHz
RBW 100 Hz
VBW 100 Hz
SPAN 10.00 kHz
SWP 802 ms
MKR
-
63.17 dB
1.00 kHz
VAVG 24
10 dB/
MKR
1.00 kHz
-
63.17 dB
D
MB15F83UL
24
PLL Lock Up time
1733 MHz
1803 MHz within
1 kHz
Lch
Hch
189
s
PLL Lock Up time
1803 MHz
1733 MHz within
1 kHz
Hch
Lch
167
s
1.733004500 GH
z
1.733000500 GH
z
1.732996500 GH
z
-
956
s
1.544 ms
500.0
s/div
4.044 ms
1.803004500 GH
z
1.803000500 GH
z
1.802996500 GH
z
-
956
s
1.544 ms
500.0
s/div
4.044 ms
MB15F83UL
25
s
s
s
s
APPLICATION EXAMPLE
0.1
F
18
17
20
19
16
15
14
13
12
11
3
4
1
2
5
6
7
8
9
10
1000 pF
1000 pF
OUTPUT
3.0 V
MB15F83UL
1000 pF
1000 pF
1000 pF
3.0 V
0.1
F
0.1
F
OUTPUT
Lock Det.
VCO
LPF
VCO
LPF
TCXO
D
ORF
PS
RF
Vp
RF
Xfin
RF
GND
RF
V
CCRF
fin
RF
LE
DATA
Clock
D
OIF
PS
IF
Vp
IF
LD/fout
V
CCIF
fin
IF
Xfin
IF
GND
IF
OSC
IN
GND
3.0 V
0.1
F
3.0 V
from controller
Notes:
Schmit trigger circuit is provided (insert a pull-up or pull-down resistor to prevent oscillation
when open-circuited in the input) .
TSSOP-20
MB15F83UL
26
s
s
s
s
USAGE PRECAUTIONS
(1) V
CCRF
, Vp
RF
, V
CCIF
and Vp
IF
must be equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to V
CCRF
, Vp
RF
, V
CCIF
and Vp
IF
to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
s
s
s
s
ORDERING INFORMATION
Part number
Package
Remarks
MB15F83ULPFT
20-pin plastic TSSOP
(FPT-20P-M06)
MB15F83ULPVA
20-pad plastic BCC
(LCC-20P-M05)
MB15F83UL
27
s
s
s
s
PACKAGE DIMENSIONS
(Continued)
20-pin Plastic TSSOP
(FPT-20P-M06)
* : These dimensions do not include resin protrusion.
Dimensions in mm (inches)
C
1999 FUJITSU LIMITED F20026S-2C-2
6.500.10(.256.004)
*
4.400.10
6.400.20
(.252.008)
(.173.004)
*
0.10(.004)
0.65(.026)
0.240.08
(.009.003)
1
10
20
11
"A"
0.170.05
(.007.002)
M
0.13(.005)
Details of "A" part
0~8
(.018/.030)
0.45/0.75
(0.50(.020))
0.25(.010)
(.041.002)
1.050.05
(Mounting height)
0.07
+0.03
0.07
+.001
.003
.003
(Stand off)
LEAD No.
INDEX
MB15F83UL
28
(Continued)
20-pad plastic BCC
(LCC-20P-M05)
Dimensions in mm (inches)
C
2001 FUJITSU LIMITED C20056S-c-2-1
3.600.10(.142.004)
11
16
1
6
11
16
1
6
3.400.10
(.134.004)
INDEX AREA
0.05(.002)
0.550.05
0.0750.025
(Stand off)
0.250.10
(.010.004)
TYP
0.50(.020)
3.00(.118)TYP
2.80(.110)REF
TYP
0.50(.020)
(.010.004)
0.250.10
2.70(.106)
TYP
"D"
"B"
"A"
"C"
0.600.10
(.024.004)
0.500.10
(.020.004)
Details of "A" part
(.020.004)
0.500.10
0.300.10
(.012.004)
Details of "B" part
Details of "C" part
(.020.004)
0.500.10
(.024.004)
0.600.10
C0.20(.008)
Details of "D" part
0.400.10
(.016.004)
0.300.10
(.012.004)
(.003.001)
(Mounting height)
(.022.002)
MB15F83UL
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0107
FUJITSU LIMITED Printed in Japan
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