Электронный компонент: MC68HC08AS20FN

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Document Outline

List of Sections
Table of Contents
List of Figures
List of Tables
Section 1. General Description
- 1.1 Contents
- 1.2 Introduction
- 1.3 Features
- 1.4 MCU Block Diagram
- 1.5 Pin Assignments
Section 2. Memory Map
- 2.1 Contents
- 2.2 Introduction
- 2.3 Input/Output (I/O) Section
Section 3. Random-Access Memory (RAM)
- 3.1 Contents
- 3.2 Introduction
- 3.3 Functional Description
Section 4. Read-Only Memory (ROM)
- 4.1 Contents
- 4.2 Introduction
- 4.3 Functional Description
Section 5. Mask Options
- 5.1 Contents
- 5.2 Introduction
- 5.3 Functional Description
- 5.4 Mask Option Register
Section 6. Electrically Erasable Programmable ROM (EEPROM)
- 6.1 Contents
- 6.2 Introduction
- 6.3 Features
- 6.4 Functional Description
Section 7. Central Processor Unit (CPU)
- 7.1 Contents
- 7.2 Introduction
- 7.3 Features
- 7.4 CPU Registers
- 7.5 Arithmetic/Logic Unit (ALU)
- 7.6 CPU During Break Interrupts
- 7.7 Instruction Set Summary
- 7.8 Opcode Map
Section 8. Clock Generator Module (CGM)
- 8.1 Contents
- 8.2 Introduction
- 8.3 Features
- 8.4 Functional Description
- 8.5 I/O Signals
- 8.6 CGM Registers
- 8.7 Interrupts
- 8.8 Special Modes
  - 8.8.1 Wait Mode
  - 8.8.2 Stop Mode
- 8.9 CGM During Break Interrupts
- 8.10 Acquisition/Lock Time Specifications
Section 9. System Integration Module (SIM)
- 9.1 Contents
- 9.2 Introduction
- 9.3 SIM Bus Clock Control and Generation
- 9.4 Reset and System Initialization
  - 9.4.1 External Pin Reset
  - 9.4.2 Active Resets from Internal Sources
- 9.5 SIM Counter
- 9.6 Program Exception Control
- 9.7 Low-Power Modes
  - 9.7.1 Wait Mode
  - 9.7.2 Stop Mode
- 9.8 SIM Registers
Section 10. Low-Voltage Inhibit (LVI)
- 10.1 Contents
- 10.2 Introduction
- 10.3 Features
- 10.4 Functional Description
  - 10.4.1 Polled LVI Operation
  - 10.4.2 Forced Reset Operation
- 10.5 LVI Status Register
- 10.6 LVI Interrupts
- 10.7 Low-Power Modes
  - 10.7.1 Wait Mode
  - 10.7.2 Stop Mode
Section 11. Break Module (Break)
- 11.1 Contents
- 11.2 Introduction
- 11.3 Features
- 11.4 Functional Description
- 11.5 Break Module Registers
  - 11.5.1 Break Status and Control Register
  - 11.5.2 Break Address Registers
- 11.6 Low-Power Modes
  - 11.6.1 Wait or Stop Mode
Section 12. Monitor ROM (MON)
- 12.1 Contents
- 12.2 Introduction
- 12.3 Features
- 12.4 Functional Description
Section 13. Computer Operating Properly (COP)
- 13.1 Contents
- 13.2 Introduction
- 13.3 Functional Description
- 13.4 I/O Signals
- 13.5 COP Control Register
- 13.6 Interrupts
- 13.7 Monitor Mode
- 13.8 Low-Power Modes
  - 13.8.1 Wait Mode
  - 13.8.2 Stop Mode
- 13.9 COP Module During Break Interrupts
Section 14. External Interrupt (IRQ)
- 14.1 Contents
- 14.2 Introduction
- 14.3 Features
- 14.4 Functional Description
- 14.5 IRQ Pin
- 14.6 IRQ Module During Break Interrupts
- 14.7 IRQ Status and Control Register
Section 15. Input/Output (I/O) Ports
- 15.1 Contents
- 15.2 Introduction
- 15.3 Port A
  - 15.3.1 Port A Data Register
  - 15.3.2 Data Direction Register A
- 15.4 Port B
  - 15.4.1 Port B Data Register
  - 15.4.2 Data Direction Register B
- 15.5 Port C
  - 15.5.1 Port C Data Register
  - 15.5.2 Data Direction Register C
- 15.6 Port D
  - 15.6.1 Port D Data Register
  - 15.6.2 Data Direction Register D
- 15.7 Port E
  - 15.7.1 Port E Data Register
  - 15.7.2 Data Direction Register E
- 15.8 Port F
  - 15.8.1 Port F Data Register
  - 15.8.2 Data Direction Register F
Section 16. Timer Interface (TIM)
- 16.1 Contents
- 16.2 Introduction
- 16.3 Features
- 16.4 Functional Description
- 16.5 Interrupts
- 16.6 Low-Power Modes
  - 16.6.1 Wait Mode
  - 16.6.2 Stop Mode
- 16.7 TIM During Break Interrupts
- 16.8 I/O Signals
  - 16.8.1 TIM Clock Pin (PTD6/ATD14/TCLK)
  - 16.8.2 TIM Channel I/O Pins (PTF3/TCH5-PTF0/TCH2 and PTE3/TCH1-PTE2/TCH0)
- 16.9 I/O Registers
Section 17. Serial Communications Interface (SCI)
- 17.1 Contents
- 17.2 Introduction
- 17.3 Features
- 17.4 Functional Description
- 17.5 Receiver Interrupts
  - 17.5.1 Error Interrupts
- 17.6 Low-Power Modes
  - 17.6.1 Wait Mode
  - 17.6.2 Stop Mode
- 17.7 SCI During Break Module Interrupts
- 17.8 I/O Signals
  - 17.8.1 PTE0/TxD (Transmit Data)
  - 17.8.2 PTE1/RxD (Receive Data)
- 17.9 I/O Registers
Section 18. Serial Peripheral Interface (SPI)
- 18.1 Contents
- 18.2 Introduction
- 18.3 Features
- 18.4 Pin Name and Register Name Conventions
- 18.5 Functional Description
  - 18.5.1 Master Mode
  - 18.5.2 Slave Mode
- 18.6 Transmission Formats
- 18.7 Error Conditions
  - 18.7.1 Overflow Error
  - 18.7.2 Mode Fault Error
- 18.8 Interrupts
- 18.9 Queuing Transmission Data
- 18.10 Resetting the SPI
- 18.11 Low-Power Modes
  - 18.11.1 Wait Mode
  - 18.11.2 Stop Mode
- 18.12 SPI During Break Interrupts
- 18.13 I/O Signals
- 18.14 I/O Registers
Section 19. Analog-to-Digital Converter (ADC)
- 19.1 Contents
- 19.2 Introduction
- 19.3 Features
- 19.4 Functional Description
- 19.5 Interrupts
- 19.6 Low-Power Modes
  - 19.6.1 Wait Mode
  - 19.6.2 Stop Mode
- 19.7 I/O Signals
- 19.8 I/O Registers
Section 20. Byte Data Link Controller-Digital (BDLC-D)
- 20.1 Contents
- 20.2 Introduction
- 20.3 Features
- 20.4 Functional Description
  - 20.4.1 BDLC Operating Modes
- 20.5 BDLC MUX Interface
- 20.6 BDLC Protocol Handler
- 20.7 BDLC CPU Interface
- 20.8 Low-Power Modes
  - 20.8.1 Wait Mode
  - 20.8.2 Stop Mode
Section 21. Electrical Specifications
- 21.1 Contents
- 21.2 Maximum Ratings
- 21.3 Functional Operating Range
- 21.4 Thermal Characteristics
- 21.5 5.0 Volt DC Electrical Characteristics
- 21.6 Control Timing
- 21.7 ADC Characteristics
- 21.8 5.0 Vdc � 10% Serial Peripheral Interface (SPI) Timing
- 21.9 CGM Operating Conditions
- 21.10 CGM Component Information
- 21.11 CGM Acquisition/Lock Time Information
- 21.12 Timer Module Characteristics
- 21.13 Memory Characteristics
- 21.14 BDLC Transmitter VPW Symbol Timings
- 21.15 BDLC Receiver VPW Symbol Timings
- 21.16 BDLC Transmitter DC Electrical Characteristics
- 21.17 BDLC Receiver DC Electrical Characteristics
Section 22. Mechanical Specifications
- 22.1 Contents
- 22.2 Introduction
- 22.3 52-Pin Plastic Leaded Chip Carrier Package (Case 778)
Section 23. Ordering Information
- 23.1 Contents
- 23.2 Introduction
- 23.3 MCU Ordering Forms
- 23.4 Application Program Media
- 23.5 ROM Program Verification
- 23.6 ROM Verification Units (RVUs)
- 23.7 MC Order Numbers

M68HC08
Microcontrollers

freescale.com

MC68HC08AS20
Data Sheet

Rev. 4.1
MC68HC08AS20/D
July 13, 2005

MC68HC08AS20

Rev. 4.1

Advance Information

Freescale Semiconductor

NON-DISCLOSURE AGREEMENT REQUIRED

Advance Information -- MC68HC08AS20

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Section 3. Random-Access Memory (RAM) . . . . . . . . . . . . . . . 51

Section 4. Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . 53

Section 5. Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Section 6. Electrically Erasable

Programmable ROM (EEPROM) . . . . . . . . . . . . 59

Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . 71

Section 8. Clock Generator Module (CGM) . . . . . . . . . . . . . . . 89

Section 9. System Integration Module (SIM) . . . . . . . . . . . . . . 117

Section 10. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . 141

Section 11. Break Module (Break) . . . . . . . . . . . . . . . . . . . . . . 147

Section 12. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . 153

Section 13. Computer Operating Properly (COP). . . . . . . . . . 163

Section 14. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . 169

Section 15. Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . 177

Section 16. Timer Interface (TIM) . . . . . . . . . . . . . . . . . . . . . . . 199

Section 17. Serial Communications Interface (SCI) . . . . . . . . 231

Section 18. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . 271

NON-DISCLOSURE AGREEMENT REQUIRED

Advance Information

MC68HC08AS20

Rev. 4.1

Freescale Semiconductor

Section 19. Analog-to-Digital Converter (ADC) . . . . . . . . . . . 305

Section 20. Byte Data Link Controller�Digital (BDLC�D) . . . . . 317

Section 21. Electrical Specifications . . . . . . . . . . . . . . . . . . . . 365

Section 22. Mechanical Specifications . . . . . . . . . . . . . . . . . . 379

Section 23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 381

MC68HC08AS20

Rev. 4.1

Advance Information

Freescale Semiconductor

NON-DISCLOSURE AGREEMENT REQUIRED

Advance Information -- MC68HC08AS20

Table of Contents

Section 1. General Description

1.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.4

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.5

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.5.1

Power Supply Pins (V

and V

) . . . . . . . . . . . . . . . . . . . 32

1.5.2

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . 33

1.5.3

External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.5.4

External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . 33

1.5.5

Analog Power Supply Pin (V

DDA

DDAREF

). . . . . . . . . . . . . 33

1.5.6

Analog Ground Pin (V

SSA

REFL

) . . . . . . . . . . . . . . . . . . . . 33

1.5.7

External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . . 34

1.5.8

Port A Input/Output (I/O) Pins (PTA7�PTA0) . . . . . . . . . . . 34

1.5.9

Port B I/O Pins (PTB7/ATD7�PTB0/ATD0). . . . . . . . . . . . . 34

1.5.10

Port C I/O Pins (PTC4�PTC0). . . . . . . . . . . . . . . . . . . . . . . 34

1.5.11

Port D I/O Pins (PTD6/ATD14/TCLKA�PTD0/ATD8) . . . . . 34

1.5.12

Port E I/O Pins (PTE7/SPSCK�PTE0/TxD) . . . . . . . . . . . . 35

1.5.13

Port F I/O Pins (PTF3/TCH5�PTF0/TCH2) . . . . . . . . . . . . . 35

1.5.14

J1850 Transmit Pin Digital (BDTxD) . . . . . . . . . . . . . . . . . . 35

1.5.15

J1850 Receive Pin Digital (BDRxD) . . . . . . . . . . . . . . . . . . 35

Section 2. Memory Map

2.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.3

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42