Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Freescale Semiconductor
Technical Data
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
Document Number: MC13202
Rev. 0.0, 03/2006
MC13202/203
Package Information
Plastic Package
Case 1311-03
Ordering Information
Device
Device Marking
Package
MC13202
13202
QFN-32
MC13203
13203
QFN-32
1
Introduction
The MC13202 and MC13203 are short range, low
power, 2.4 GHz Industrial, Scientific, and Medical
(ISM) band transceivers. The MC13202/MC13203
contain a complete 802.15.4 physical layer (PHY)
modem designed for the IEEE
802.15.4 wireless
standard which supports peer-to-peer, star, and mesh
networking.
The MC13202 includes the 802.15.4 PHY/MAC for use
with the HCS08 Family of MCUs. The MC13203 also
includes the 802.15.4 PHY/MAC plus the ZigBee
Protocol Stack for use with the HCS08 Family of MCUs.
With the exception of the addition of the ZigBee Protocol
Stack, the MC13203 functionality is the same as the
MC13202.
When combined with an appropriate microcontroller
(MCU), the MC13202/MC13203 provides a
cost-effective solution for short-range data links and
networks. Interface with the MCU is accomplished using
a four wire serial peripheral interface (SPI) connection
and an interrupt request output which allows for the use
of a variety of processors. The software and processor
MC13202/203
2.4 GHz Low Power Transceiver
for the IEEE
802.15.4 Standard
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4
4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 6
5 Electrical Characteristics . . . . . . . . . . . . . . . 8
6 Functional Description . . . . . . . . . . . . . . . . 11
7 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14
8 Crystal Oscillator Reference Frequency . . 18
9 Transceiver RF Configurations and
External Connections . . . . . . . . . . . . . . . . . 21
10Packaging Information . . . . . . . . . . . . . . . . 28
MC13202/203 Technical Data, Rev. 0.0
2
Freescale Semiconductor
can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBeeTM
networking.
Applications include, but are not limited to, the following:
Residential and commercial automation
-- Lighting control
-- Security
-- Access control
-- Heating, ventilation, air-conditioning (HVAC)
-- Automated meter reading (AMR)
Industrial Control
-- Asset tracking and monitoring
-- Homeland security
-- Process management
-- Environmental monitoring and control
-- HVAC
-- Automated meter reading
Health Care
-- Patient monitoring
-- Fitness monitoring
The transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RF
transmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO),
on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports
250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with
5.0 MHz channel spacing per the IEEE 802.15.4 specification. The SPI port and interrupt request output
are used for receive (RX) and transmit (TX) data transfer and control.
2
Features
Recommended power supply range: 2.0 to 3.4 V
Fully compliant IEEE 802.15.4 transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels
and full spread-spectrum encode and decode
Operates on one of 16 selectable channels in the 2.4 GHz band
-1 to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical
Receive sensitivity of <-92 dBm (typical) at 1% PER, 20-byte packet, much better than the IEEE
802.15.4 specification of -85 dBm
Integrated transmit/receive switch
Dual PA output pairs which can be programmed for full differential single port or dual port
operation that supports an external LNA and/or PA
Three power down modes for increased battery life
MC13202/203 Technical Data, Rev. 0.0
Freescale Semiconductor
3
-- < 1 A Off current
-- 1.0 A Typical Hibernate current
-- 35 A Typical Doze current (no CLKO)
Programmable frequency clock output (CLKO) for use by MCU
Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external
variable capacitors and allows for automated production frequency calibration
Four internal timer comparators available to supplement MCU timer resources
Supports both Packet Mode and Streaming Mode data transfer
Buffered transmit and receive data packets for simplified use with low cost MCUs
Seven GPIO to supplement MCU GPIO
Operating temperature range: -40 C to 85 C
Small form factor QFN-32 Package
-- Meets moisture sensitivity level (MSL) 3
-- 260 C peak reflow temperature
-- Meets lead-free requirements
2.1
Software Features
Freescale provides a wide range of software functionality to complement the MC13202/203 hardware.
There are three levels of application solutions:
1. Simple proprietary wireless connectivity.
2. User networks built on the IEEE 802.15.4 MAC standard.
3. ZigBee-compliant network stack.
2.1.1
Simple MAC (SMAC)
Small memory footprint (about 3 Kbytes typical)
Supports point-to-point and star network configurations
Proprietary networks
Source code and application examples provided
2.1.2
IEEE 802.15.4-Compliant MAC
Supports star, mesh and cluster tree topologies
Supports beaconed networks
Supports GTS for low latency
Multiple power saving modes (idle doze, hibernate)
2.1.3
ZigBee-Compliant Network Stack
Supports ZigBee 1.0 specification
MC13202/203 Technical Data, Rev. 0.0
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Freescale Semiconductor
Supports star, mesh and tree networks
Advanced Encryption Standard (AES) 128-bit security
3
Block Diagrams
Figure 1
shows a simplified block diagram of the MC13202/MC13203 which is an IEEE Standard
802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY)
specification.
Figure 2
shows the basic system block diagram for the MC13202/MC13203 in an
application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request
line. The media access control (MAC), drivers, and network and application software (as required) reside
on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor
depending on application requirements.
Figure 1. 802.15.4 modem Simplified Block Diagram
Phase Shift Modulator
RST
GPIO1
GPIO2
GPIO3
GPIO4
XTAL2
XTAL1
RFIN_M
(PAO_M)
PAO_P
PAO_M
MOSI
MISO
SPICLK
RXTXEN
CE
ATTN
GPIO5
GPIO6
GPIO7
Receive
Packet RAM
Transmit
Packet RAM 1
Transmit RAM
Arbiter
Receiv e RAM
Arbiter
PA
VCO
Crystal
Oscillator
Sy mbol
Generation
FCS
Generation
Header
Generation
MUX
Sequence
Manager
(Control Logic)
VDDLO2
4
256 MHz
2.45 GHz
LNA
1st IF Mix er
IF = 65 MHz
2nd IF Mix er
IF = 1 MHz PMA
Decimation
Filter
Matched
Filter
Baseband
Mix er
DCD
C
o
rr
el
at
or
Sy
m
b
o
l
Sy
n
c
h &
D
e
t
CCA
Packet
Processor
IRQ
Arbiter
24 Bit Ev ent Timer
IRQ
16 MHz
AGC
Analog
Regulator
VBATT
Digital
Regulator L
Digital
Regulator H
Power-Up
Control
Logic
Cry stal
Regulator
VCO
Regulator
VDDINT
Programmable
Prescaler
CLKO
4 Programmable
Timer Comparators
Synthesizer
VDDD
VDDVCO
SE
R
I
AL
P
E
R
I
P
HE
RA
L
IN
T
E
R
F
A
C
E
(
SPI
)
VDDA
VDDLO1
Transmit
Packet RAM 2
T / R
RFIN_P
(PAO_P)
CT_Bias
MC13202/203 Technical Data, Rev. 0.0
Freescale Semiconductor
5
Figure 2. System Level Block Diagram
4
Data Transfer Modes
The MC13202/MC13203 has two data transfer modes:
1. Packet Mode -- Data is buffered in on-chip RAM
2. Streaming Mode -- Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1
Packet Structure
Figure 3
shows the packet structure of the MC13202/MC13203. Payloads of up to 125 bytes are supported.
The MC13202/MC13203 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and
appended to the end of the data.
Figure 3. MC13202/MC13203 Packet Structure
4.2
Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
Analog
Receiv er
MC13202/MC13203
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Pow er Up
Management
Control
Logic
Buffer RAM
D
i
git
a
l T
r
a
n
s
c
e
iv
er
SPI
and GPIO
Microcontroller
SPI
ROM
(Flash)
RAM
CPU
A/D
Ti
me
r
Application
IR
Q
A
r
b
i
te
r
RA
M A
r
b
i
t
e
r
Ti
m
e
r
Netw ork
MAC
PHY Driv er
Preamble
SFD
FLI
Payload Data
FCS
4 bytes
1 byte
1 byte
125 bytes maximum
2 bytes
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