Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
Freescale Semiconductor
Technical Data
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
Document Number: MC13191
Rev. 1.3, 08/2005
MC13191
Package Information
Plastic Package
Case 1311-03
(QFN-32)
(Scale 1:1)
Ordering Information
Device
Device Marking
Package
MC13191
13191
QFN-32
1 Introduction
The MC13191 is a short range, low power, 2.4 GHz
Industrial, Scientific, and Medical (ISM) band
transceivers. The MC13191 contains a complete packet
data modem which is compliant with the IEEE
802.15.4 Standard PHY (Physical) layer. This allows the
development of proprietary point-to-point and star
networks based on the 802.15.4 packet structure and
modulation format. For full 802.15.4 compliance, the
MC13192 and Freescale's 802.15.4 MAC software are
required.
When combined with an appropriate microcontroller
(MCU), the MC13191 provides a cost-effective solution
for short-range data links and networks. Interface with
the MCU is accomplished using a four wire serial
peripheral interface (SPI) connection and an interrupt
request output which allows for the use of a variety of
processors. The software and processor can be scaled to
fit applications ranging from simple point-to-point to star
networks.
MC13191
2.4 GHz ISM Band Low Power
Transceiver
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 3
4 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . 3
5 Electrical Characteristics . . . . . . . . . . . . . . . 7
6 Functional Description . . . . . . . . . . . . . . . . 11
7 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 15
8 Applications Information . . . . . . . . . . . . . . . 18
9 Packaging Information . . . . . . . . . . . . . . . . . 23
MC13191 Technical Data, Rev. 1.3
2
Freescale Semiconductor
Features
For more detailed information about MC13191 operation, refer to the MC13191 Reference Manual, part
number MC13191RM.
Applications include, but are not limited to, the following:
Remote control and wire replacement in industrial systems such as wireless sensor networks
Factory automation and motor control
Energy Management (lighting, HVAC, etc.)
Asset tracking and monitoring
Potential consumer applications include:
Home automation and control (lighting, thermostats, etc.)
Human interface devices (keyboard, mice, etc.)
Remote entertainment control
Wireless toys
The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator
(VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device
supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with
5.0 MHz channel spacing. The SPI port and interrupt request output are used for receive (RX) and transmit
(TX) data transfer and control.
2 Features
IEEE 802.15.4 PHY Compliant
-- 16 Channels
-- Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode/decode
-- RX sensitivity of -91 dBm (typical) at 1.0% packet error rate
Recommended power supply range: 2.0 to 3.4 V
0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power
Buffered transmit and receive data packets for simplified use with low cost MCUs
Three power down modes for power conservation:
-- < 1.0 A Off current
-- 2.3 A Typical Hibernate current
-- 35 A Typical Doze current (no CLKO)
Two internal timer comparators available to reduce MCU resource requirements
Programmable frequency clock output for use by MCU
Onboard trim capability for 16 MHz crystal reference oscillator eliminates the need for external
variable capacitors and allows for automated production frequency calibration.
Seven general purpose input/output (GPIO) signals
Operating temperature range: -40 C to 85 C
Small form factor QFN-32 Package
Block Diagrams
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
3
-- RoHS compliant
-- Meets moisture sensitivity level (MSL) 3
-- 260 C peak reflow temperature
-- Meets lead-free requirements
3 Block Diagrams
Figure 2
shows a simplified block diagram of the MC13191 transceiver that meets the requirements of the
IEEE 802.15.4 PHY.
Figure 3
shows the basic system block diagram for the MC13191 in an application.
Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The
media access control (MAC), drivers, and network and application software (as required) reside on the
host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor
depending on application requirements.
4 Data Transfer Mode
The MC13191 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet
RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits
wide.
4.1 Packet Structure
Figure 4
shows the packet structure of the MC13191 which is consistent with the IEEE 802.15.4 Standard.
Payloads of up to 125 bytes are supported. The MC13191 adds a four-byte preamble, a one-byte Start of
Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame
Check Sequence (FCS) is calculated and appended to the end of the data.
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. An Energy Detect can be performed based upon the baseband energy
integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD),
the correlator "de-spreads" the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal,
determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 s period after the packet preamble and stored in RAM.
The MC13191 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet
RAM. The MCU is notified that an entire packet has been received via an interrupt.
MC13191 Technical Data, Rev. 1.3
4
Freescale Semiconductor
Data Transfer Mode
Figure 1
shows energy detection reported power versus input power. Note that the IEEE 802.15.4 Standard
accuracy and range limits are shown for reference.
Figure 1. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
-85
-75
-65
-55
-45
-35
-25
-85
-75
-65
-55
-45
-35
-25
-15
Input Pow er Level (dBm)
R
e
po
r
t
ed
P
o
w
e
r
L
e
v
e
l
(
d
B
m
)
802.15.4 Accuracy
and Range Requirements
Data Transfer Mode
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
5
4.3 Transmit Path Description
For the transmit path, the TX data that was previously stored in TX PAcket RAM is retrieved, formed into
packets, spread, and then up-converted to the transmit frequency.
Because the MC13191 is used in packet mode, data is processed as an entire packet. The data is first loaded
into the TX buffer. The MCU then requests that the MC13191 transmit the data. The MCU is notified via
an interrupt when the whole packet has successfully been transmitted.
Figure 2. MC13191 Simplified Block Diagram
P has e S hift M odulator
R ST
G PIO 1
G PIO 2
G PIO 3
G PIO 4
XT A L2
XT A L1
R F IN -
R F IN +
P AO +
PAO -
M O SI
M ISO
SP IC LK
R XT XEN
C E
AT T N
G PIO 5
G PIO 6
G PIO 7
R ec eiv e
Pac k et R A M
T rans m it
P ac k et R AM 1
T rans m it R AM
Arbiter
R ec eiv e R AM
Arbiter
P A
V CO
Cry s tal
O s c illator
S y m bol
G eneration
F C S
G eneration
Header
G eneration
MU
X
Sequenc e
M anager
(C ontrol Logic )
V DD LO 2
4
256 M Hz
2.45 G Hz
LN A
1s t IF M ix er
IF = 65 M Hz
2nd IF M ix er
IF = 1 M Hz
PM A
Dec im ation
F ilter
M atc hed
F ilter
Bas eband
M ix er
DC D
C
o
r
r
elat
or
S
y
m
bol
S
y
nc
h &
D
e
t
C C A
Pac k et
P roc es s or
IR Q
A rbiter
24 Bit Ev ent T im er
IR Q
16 M Hz
AG C
Analog
R egulator
VBA T T
Digital
R egulator L
Digital
R egulator H
Pow er-U p
C ontrol
Logic
C ry s tal
R egulator
VC O
R egulator
VDDIN T
Program m able
Pres c aler
C LKO
2 Program m able
T im er C om parators
Sy nthesizer
VDDD
VDDVC O
SE
R
I
A
L
PE
R
I
PH
ER
A
L
IN
TE
R
F
A
C
E
(SP
I
)
V DDA
VDDLO 1
MC13191 Technical Data, Rev. 1.3
6
Freescale Semiconductor
Data Transfer Mode
Figure 3. System Level Block Diagram
Figure 4. MC13191 Packet Structure
Analog Receiver
MC13191
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Power Up
Management
Control
Logic
Buffer RAM
Dig
i
ta
l
T
r
an
sc
e
i
ve
r
SPI
and GPIO
Microcontroller
SPI
ROM
(Flash)
RAM
CPU
A/D
Ti
m
e
r
Application
IR
Q Ar
b
i
te
r
RA
M Ar
b
i
t
e
r
Tim
e
r
Network
MAC
PHY Driver
Preamble
SFD
FLI
Payload Data
FCS
4 bytes
1 byte
1 byte
125 bytes maximum
2 bytes
Electrical Characteristics
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
7
5 Electrical Characteristics
5.1 Maximum Ratings
5.2 Recommended Operating Conditions
Table 1. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Power Supply Voltage
V
BATT,
V
DDINT
3.6
Vdc
RF Input Power
P
max
10
dBm
Junction Temperature
T
J
125
C
Storage Temperature Range
T
stg
-55 to 125
C
Note: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
or Recommended Operating Conditions tables.
Note: Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFIN = 100 V MM,
PAO = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection.
Table 2. Recommended Operating Conditions
Characteristic Symbol
Min
Typ
Max
Unit
Power Supply Voltage (V
BATT
= V
DDINT
)
V
BATT,
V
DDINT
2.0
2.7
3.4
Vdc
Input Frequency
f
in
2.405
-
2.480
GHz
Ambient Temperature Range
T
A
-40
25
85
C
Logic Input Voltage Low
V
IL
0
-
30%
V
DDINT
V
Logic Input Voltage High
V
IH
70%
V
DDINT
-
V
DDINT
V
SPI Clock Rate
f
SPI
-
-
8.0
MHz
RF Input Power
P
max
-
-
10
dBm
Crystal Reference Oscillator Frequency (40 ppm over
operating conditions to meet the 802.15.4 standard.)
f
ref
16 MHz Only
MC13191 Technical Data, Rev. 1.3
8
Freescale Semiconductor
Electrical Characteristics
5.3 DC Electrical Characteristics
Table 3. DC Electrical Characteristics
(V
BATT
, V
DDINT
= 2.7 V, T
A
= 25 C, unless otherwise noted)
Characteristic Symbol
Min
Typ
Max
Unit
Power Supply Current (V
BATT
+ V
DDINT
)
Off
Hibernate
Doze (No CLKO)
Idle
Transmit Mode
Receive Mode
I
leakage
I
CCH
I
CCD
I
CCI
I
CCT
I
CCR
-
-
-
-
-
-
0.2
2.3
35
500
30
37
2.5
22.0
154
1500
38
45
A
A
A
A
mA
mA
Input Current (V
IN
= 0 V or V
DDINT
) (All digital inputs)
I
IN
-
-
1
A
Input Low Voltage (All digital inputs)
V
IL
0
-
30%
V
DDINT
V
Input High Voltage (all digital inputs)
V
IH
70%
V
DDINT
-
V
DDINT
V
Output High Voltage (I
OH
= -1 mA) (All digital outputs)
V
OH
80%
V
DDINT
-
V
DDINT
V
Output Low Voltage (I
OL
= 1 mA) (All digital outputs)
V
OL
0
-
20%
V
DDINT
V
Electrical Characteristics
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
9
5.4 AC Electrical Characteristics
NOTE
All AC parameters measured with SPI Registers at default settings except
where noted and the following registers over-programmed:
Register 08 = 0xFFF7 and Register 11 = 0x20FF
Table 4. Receiver AC Electrical Characteristics
(V
BATT
, V
DDINT
= 2.7 V, T
A
= 25 C, f
ref
= 16 MHz, unless otherwise noted.
Parameters measured at connector J6 of evaluation circuit.)
Characteristic Symbol
Min
Typ
Max
Unit
Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 C)
SENS
per
-
-92
-
dBm
Sensitivity for 1% Packet Error Rate (PER) (+25 C)
-
-92
-82
dBm
Saturation (maximum input level)
SENS
max
0
10
-
dBm
Channel Rejection for 1% PER (desired signal -82 dBm)
+5 MHz (adjacent channel)
-5 MHz (adjacent channel)
+10 MHz (alternate channel)
-10 MHz (alternate channel)
>= 15 MHz
-
-
-
-
-
25
31
42
41
49
-
-
-
-
-
dB
dB
dB
dB
dB
Frequency Error Tolerance (total)
-
-
200
kHz
Symbol Rate Error Tolerance
-
-
80
ppm
Table 5. Transmitter AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, fref = 16 MHz, unless otherwise noted.
Parameters measured at connector J5 of evaluation circuit.)
Characteristic Symbol
Min
Typ
Max
Unit
Power Spectral Density (-40 to +85 C) Absolute limit
-
-47
-
dBm
Power Spectral Density (-40 to +85 C) Relative limit
-
47
-
Nominal Output Power
1
1
SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical).
P
out
-5
0
-
dBm
Maximum Output Power
2
2
SPI Register 12 programmed to 0x00FC which sets output power to maximum.
4
dBm
Error Vector Magnitude
EVM
-
20
45
%
Output Power Control Range (-27 dBm to +4 dBm typical)
-
31
-
dB
Over the Air Data Rate
-
250
-
kbps
Spurious Emissions
-
-56
-40
dBm
2nd Harmonic
-
-42
-
dBc
3rd Harmonic
-
-44
-
dBc
MC13191 Technical Data, Rev. 1.3
10
Freescale Semiconductor
Electrical Characteristics
Figure 5. Parameter Evaluation Circuit
J4
CLOCK Sel
1
2
MISO
R3
10k
RXD
J2
HEADER 10X2
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
SPI_CLK
GPIO1
L2
6.8nH
T2
2450BL15B200
1
3
2
5
4
R5
47k
GPIO2
R2 200
+
C2
220pF
U1
MC13192
16
20
14
22
3
5
7
27
9
13
19
24
18
17
4
6
8
26
10
23
15
21
25
11
12
1
28
2
29
30
31
32
SPICLK
IRQ
ATTN
VDDINT
GND
PAO+
GND
XTAL2
GPIO3
RXTXEN
CE
GPIO6
MISO
MOSI
GND
PAO-
GPIO4
XTAL1
GPIO2
GPIO5
CLKO
VDDD
GPIO7
GPIO1
RST
RFIN-
VDDLO2
RFIN+
VDDLO1
VDDVCO
VBATT
VDDA
R1
47k
R6
47k
R4
47k
ABEL RESET
C7
10pF
+
C1
220pF
C4
9pF
C5
9pF
J3
Wake Up
1
2
ATTN
J6
SMA
1
2
J5
SMA
1
2
+
C3
220pF
GPIO2
J7
RESET
1
2
3
T1
2450BL15B200
1
3
2
5
4
CLKO
C8
10pF
MOSI
GPIO1
VCC
Y1
TSX-10A@16Mhz
Baud SEL
PA2
J1
MCU Interface
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
C6
0.1uF
RTXENi
L1
8.2nH
MCU RESET
CE
IRQ
RTXENi
16 MHz CLK
Functional Description
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
11
6 Functional Description
6.1 MC13191 Operational Modes
The MC13191 has a number of operational modes that allow for low-current operation. Transition from
the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the
IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along
with the transition times, in
Table 6
. Current drain in the various modes is listed in
Table 3
, DC Electrical
Characteristics.
Table 6. MC13191 Mode Definitions and Transition Times
Mode
Definition
Transition Time
To or From Idle
Off
All IC functions Off, Leakage only. RST asserted. Digital outputs are
tri-stated including IRQ
25 ms to Idle
Hibernate
Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to
ATTN. Data is retained.
20 ms to Idle
Doze
Crystal Reference Oscillator On but CLKO output available only if Register
7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds
to ATTN and can be programmed to enter Idle Mode through an internal
timer comparator.
(300 + 1/CLKO) s
to Idle
Idle
Crystal Reference Oscillator On with CLKO output available. SPI active.
Receive
Crystal Reference Oscillator On. Receiver On.
144 s from Idle
Transmit
Crystal Reference Oscillator On. Transmitter On.
144 s from Idle
MC13191 Technical Data, Rev. 1.3
12
Freescale Semiconductor
Functional Description
6.2 Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13191, checks its status, and reads/writes data to the device
through the 4-wire SPI port. The transceiver operates as an SPI slave device only. A transaction between
the host and the MC13191 occurs as multiple 8-bit bursts on the SPI. The SPI signals are:
1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13191. Data is clocked into
the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out
changes state on the trailing (falling) edge of SPICLK.
NOTE
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The MC13191 presents data to the master on the MISO output.
A typical interconnection to a microcontroller is shown in
Figure 6
.
Figure 6. SPI Interface
Although the SPI port is fully static, internal memory, timer, and interrupt arbiters require an internal clock
(CLK
core
) derived from the crystal reference oscillator, to communicate from the SPI registers to internal
registers and memory.
Shift Register
Baud Rate
Generator
Shift Register
Chip Enable (CE)
RxD
MISO
TxD
MOSI
Sclk
SPICLK
MCU
MC13191
CE
Functional Description
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
13
6.2.1
SPI Burst Operation
The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master
(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the
master on the MISO line. Although an MC13191 transaction is three or more SPI bursts long, the timing
of a single SPI burst is shown in
Figure 6
.
Figure 7. SPI Single Burst Timing Diagram.
Table 7. SPI Timing Specifications
Symbol
Parameter
Min
Typ
Max
Unit
T0
SPICLK period
125
nS
T1
Pulse width, SPICLK low
62.5
nS
T2
Pulse width, SPICLK high
62.5
nS
T3
Delay time, MISO data valid from falling
SPICLK
15
nS
T4
Setup time, CE low to rising SPICLK
15
nS
T5
Delay time, MISO valid from CE low
15
nS
T6
Setup time, MOSI valid to rising SPICLK
15
nS
T7
Hold time, MOSI valid from rising SPICLK
15
nS
1
2
3
4
5
6
7
8
CE
SPICLK
T1
T2
T4
T0
SPI Burst
Valid
T5
T6
T3
Valid
T7
MISO
MOSI
Valid
MC13191 Technical Data, Rev. 1.3
14
Freescale Semiconductor
Functional Description
6.2.2 SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13191 requires that a complete
SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion
of CE to low, signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the
transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and
identifies the access as being a read or write operation. In this context, a write consists of data written to
the MC13191 and a read consists of data written to the SPI master. The following SPI bursts will be either
the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).
Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13191
never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to
a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal
the end of the transaction. Refer to the MC13191 Reference Manual, part number MC13191RM for more
details on SPI registers and transaction types.
An example SPI read transaction with a 2-byte payload is shown in
Figure 8
.
Figure 8. SPI Read Transaction Diagram
CE
SPICLK
MISO
MOSI
Valid
Valid
Valid
Clock Burst
Header
Read data
Pin Connections
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
15
7 Pin Connections
Table 8. Pin Function Description
Pin #
Pin Name
Type
Description
Functionality
1
RFIN-
RF Input
LNA negative differential input.
2
RFIN+
RF Input
LNA positive differential input.
3
Not Used
Tie to Ground.
4
Not Used
Tie to Ground.
5
PAO+
RF Output /DC Input Power Amplifier Positive Output. Open
drain. Connect to V
DDA
.
6
PAO-
RF Output/DC Input Power Amplifier Negative Output. Open
drain. Connect to V
DDA
.
7
SM
Test mode pin. Tie to Ground
Tie to Ground for normal
operation
8
GPIO4
1
Digital Input/ Output General Purpose Input/Output 4.
See Footnote 1
9
GPIO3
1
Digital Input/ Output General Purpose Input/Output 3.
See Footnote 1
10
GPIO2
1
Digital Input/ Output General Purpose Input/Output 2. When
gpio_alt_en, Register 9, Bit 7 = 1, GPIO2
functions as a "CRC Valid" indicator.
See Footnote 1
11
GPIO1
1
Digital Input/ Output General Purpose Input/Output 1. When
gpio_alt_en, Register 9, Bit 7 = 1, GPIO1
functions as an "Out of Idle" indicator.
See Footnote 1
12
RST
Digital Input
Active Low Reset. While held low, the IC
is in Off Mode and all internal information
is lost from RAM and SPI registers.
When high, IC goes to IDLE Mode, with
SPI in default state.
13
RXTXEN
Digital Input
Active High. Low to high transition
initiates RX or TX sequence depending
on SPI setting. Should be taken high after
SPI programming to start RX or TX
sequence and should be held high
through the sequence. After sequence is
complete, return RXTXEN to low. When
held low, forces Idle Mode.
14
ATTN
Digital Input
Active Low Attention. Transitions IC from
either Hibernate or Doze Modes to Idle.
15
CLKO
Digital Output
Clock output to host MCU.
Programmable frequencies of:
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz,
62.5 kHz, 32.786+ kHz (default),
and 16.393+ kHz.
16
SPICLK
Digital Clock Input
External clock input for the SPI interface.
17
MOSI
Digital Input
Master Out/Slave In. Dedicated SPI data
input.
MC13191 Technical Data, Rev. 1.3
16
Freescale Semiconductor
Pin Connections
18
MISO
Digital Output
Master In/Slave Out. Dedicated SPI data
output.
19
CE
Digital Input
Active Low Chip Enable. Enables SPI
transfers.
20
IRQ
Digital Output
Active Low Interrupt Request.
Open drain device.
Programmable 40 k
internal
pull-up.
Interrupt can be serviced every
6 s with <20 pF load.
Optional external pull-up must
be >4 k
.
21
VDDD
Power Output
Digital regulated supply bypass.
Decouple to ground.
22
VDDINT
Power Input
Digital interface supply & digital regulator
input. Connect to Battery.
2.0 to 3.4 V. Decouple to
ground.
23
GPIO5
1
Digital Input/Output General Purpose Input/Output 5.
See Footnote 1
24
GPIO6
1
Digital Input/Output General Purpose Input/Output 6.
See Footnote 1
25
GPIO7
1
Digital Input/Output General Purpose Input/Output 7.
See Footnote 1
26
XTAL1
Input
Crystal Reference oscillator input.
Connect to 16 MHz crystal and
load capacitor.
27
XTAL2
Input/Output
Crystal Reference oscillator output
Note: Do not load this pin by using it as
a 16 MHz source. Measure 16 MHz
output at Pin 15, CLKO, programmed for
16 MHz. See the
MC13191 Reference
Manual
for details.
Connect to 16 MHz crystal and
load capacitor.
28
VDDLO2
Power Input
LO2 VDD supply. Connect to VDDA
externally.
29
VDDLO1
Power Input
LO1 VDD supply. Connect to VDDA
externally.
30
VDDVCO
Power Output
VCO regulated supply bypass.
Decouple to ground.
31
VBATT
Power Input
Analog voltage regulators Input. Connect
to Battery.
Decouple to ground.
32
VDDA
Power Output
Analog regulated supply Output.
Connect to directly VDDLO1 and
VDDLO2 externally and to PAO through
a frequency trap.
Note: Do not use this pin to supply
circuitry external to the chip.
Decouple to ground.
EP
Ground
External paddle / flag ground.
Connect to ground.
1
The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins
should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state.
Table 8. Pin Function Description (continued)
Pin #
Pin Name
Type
Description
Functionality
Pin Connections
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
17
Figure 9. Pin Connections (Top View)
1
2
3
GPIO3
GPIO2
GPIO1
RST
RXT
XEN
A
TTN
CL
KO
SPICLK
4
5
6
7
8
NC
RFIN+
NC
PAO+
PAO-
NC
GPIO4
RFIN-
VDDINT
GPIO5
VDDD
IRQ
CE
MISO
MOSI
GPIO6
12
13
14
15
16
11
10
9
24
23
22
21
20
19
18
17
VDDA
VBA
T
T
VDDVCO
VDDL
O1
VDDL
O2
XT
AL2
XT
AL1
GPIO7
EP
29
28
27
26
25
30
31
32
MC13191
MC13191 Technical Data, Rev. 1.3
18
Freescale Semiconductor
Applications Information
8 Applications Information
8.1 Crystal Oscillator Reference Frequency
For low long term drift, users may require that several frequency tolerances be kept as low as
40 ppm
accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in
acceptable performance. The MC13191 transceiver provides onboard crystal trim capacitors to assist in
meeting this performance.
The primary determining factor in meeting this specification is the tolerance of the crystal oscillator
reference frequency. A number of factors exist that contribute to this tolerance and a crystal specification
will quantify each of them:
1. The initial (or make) tolerance of the crystal resonant frequency itself.
2. The variation of the crystal resonant frequency with temperature.
3. The variation of the crystal resonant frequency with time, also commonly known as aging.
4. The variation of the crystal resonant frequency with load capacitance, also commonly known as
pulling. This is affected by:
a) The external load capacitor values - initial tolerance and variation with temperature.
b) The internal trim capacitor values - initial tolerance and variation with temperature.
c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package
capacitance and stray board capacitance; and its initial tolerance and variation with
temperature.
Freescale has specified that a 16 MHz crystal with a <9 pF load capacitance is required. The MC13191
does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring
higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its
performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen
across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13191
requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors
are seen to be in series by the crystal, so each must be <18 pF for proper loading.
In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with
a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray
capacitance total value (6.8 pF) sum up to 9.2 pF for a total of 16 pF. The value for the stray capacitance
was determined empirically assuming the default internal trim capacitor value and for a specific board
layout. A different board layout may require a different external load capacitor value. The on-chip trim
capability may be used to determine the closest standard value by adjusting the trim value via the SPI and
observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately
5 pF in 20 fF steps.
Initial tolerance for the internal trim capacitance is approximately
15%.
Because the MC13191 contains an on-chip reference frequency trim capability, it is possible to trim out
virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board
basis.
Applications Information
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
19
A tolerance analysis budget may be created using all the previously stated factors. It is an engineering
judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if
the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging
factor is usually specified in ppm/year and the product designer can determine how many years are to be
assumed for the product lifetime. Taking all of the factors into account, the product designer can determine
the needed specifications for the crystal and external load capacitors to meet the desired specification.
8.2 Design Example
Figure 10
shows a basic application schematic for interfacing the MC13191 with an MCU.
Table 9
lists
the Bill of Materials (BOM).
The MC13191 has differential RF inputs and outputs that are well suited to balanced printed wire antenna
structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other
single-ended structures can be used with commercially available chip baluns or microstrip equivalents.
PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking
elements. This is accomplished through the baluns in the referenced design.
The 16 MHz crystal should be mounted close to the MC13191 because the crystal trim default assumes
that the listed KDS Daishinku crystal (see
Table 10
) and the 6.8 pF load capacitors shown are used. If a
different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of
9 pF or less. A second crystal that has been evaluated and also gives acceptable performance is the
Toyocom TSX-10A 16 MHZ TN4-26139 (see
Table 11
).
VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1
and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing
capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown.
The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency
of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is
programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven
by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter
approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line
wakes up the MC13191. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU
control. In this case, RXTXEN must be controlled by an MCU GPIO with the connection shown. Device
reset (RST) is controlled through a connection to an MCU GPIO.
MC13191 Technical Data, Rev. 1.3
20
Freescale Semiconductor
Applications Information
Figure 10. MC13191 Configured With a MCU
MCU
MOSI
IC2
PG 2012TK-E2
6
5
4
1
3
2
VDD
IN
VCONT
OUT1
OUT2
GND
50_Ohm4
C7
10pF
L2
8.2nH
ANT1
F_Antenna
X1
16.000MHz
100_Ohm3
C1
1F
VDDA
MISO
3V0_RF
SS
GPIO
GPIO
50_Ohm3
IRQ
50_Ohm1
50_Ohm2
GPIO
100_Ohm2
50_Ohm7
GPIO
R3
0
R2
0
R1
470K
C4
220nF
C12
0.5pF
VDDA
C3
220nF
C8
10pF
GPIO
Z1
LDB212G4020C-001
5
1
6
2
3
4
C2
220nF
L1
6.8nH
C6
6.8pF
C9
10pF
Z2
LDB212G4020C-001
5
1
6
2
3
4
C11
10pF
GPIO
C5
6.8pF
3V0_BB
J1
SMA Receptacle, Female
1
2
5
3
4
50_Ohm6
CLK
IC1
MC13191
14
19
15
11
10
9
8
25
23
24
20
18
17
6
5
1
2
12
13
7
16
4
3
26
27
31
32
21
22
29
28
30
EP
ATTNB
CEB
CLKO
GPIO1
GPIO2
GPIO3
GPIO4
GPIO7
GPIO5
GPIO6
IRQB
MISO
MOSI
PAO_M
PAO_P
RIN_M
RIN_P
RSTB
RXTXEN
Not Used
SPICLK
Not Used
Not Used
XTAL1
XTAL2
VBATT
VDDA
VDDD
VDDINT
VDDLO1
VDDLO2
VDDVCO
GND
100_Ohm4
L3
8.2nH
C10
10pF
SCLK
100_Ohm1
Applications Information
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
21
Table 9. MC13191 to MCU Bill of Materials (BOM)
Item
Quantity
Reference
Part
Manufacturer
1
1
ANT1
F_Antenna
Printed wire
2
1
C1
1
F
3
3
C2, C3, C4
220 nF
4
2
C5, C6
6.8 pF
5
5
C7, C8, C9, C10,
C11
10 pF
6
1
C12
0.5 pF
7
1
IC1
MC13191
Freescale Semiconductor
8
1
IC2
PG2012TK-E2
NEC
9
1
J1
SMA Receptacle,
Female
10
1
L1
6.8 nH
11
2
L2, L3
8.2 nH
12
1
R1
470 k
13
2
R2, R3
0
14
1
X1
16.000 MHz, Type
DSX321G, ZD00882
KDS, Daishinku Corp
15
2
Z1, Z2
LDB212G4020C-001
Murata
Table 10. Daishinku, KDS - DSX321G, ZD00882 Crystal Specifications
Parameter
Value
Unit
Condition
Type
DSX321G
surface mount
Frequency
16
MHz
Frequency tolerance
20
ppm
at 25 C 3 C
Equivalent series resistance
100
max
Temperature drift
20
ppm
-10 C to +60 C
Load capacitance
8.0
pF
Drive level
10
W
2
W
Shunt capacitance
2
pF
max
Mode of oscillation
fundamental
MC13191 Technical Data, Rev. 1.3
22
Freescale Semiconductor
Applications Information
Table 11. Toyocom TSX-10A 16 MHZ TN4-26139 Crystal Specifications
Parameter
Value
Unit
Condition
Type
TSX-10A
surface mount
Frequency
16
MHz
Frequency tolerance
10
ppm
at 25 C 3 C
Equivalent series resistance
40
max
Temperature drift
16
ppm
-40 C to +85 C
Load capacitance
9
pF
Drive level
100
W
max
Shunt capacitance
1.2
pF
typical
Mode of oscillation
fundamental
Packaging Information
MC13191 Technical Data, Rev. 1.3
Freescale Semiconductor
23
9 Packaging Information
Figure 11. Outline Dimensions for QFN-32, 5x5 mm
(Case 1311-03, Issue E)
N
EXPOSED DIE
ATTACH PAD
2.95
25
8
1
32
3.25
32X
0.18
0.30
24
17
16
9
0.5
M
0.1
C
M
0.05
C
A
B
32X
0.5
0.3
C
0.1
A
B
C
0.1
A
B
VIEW M-M
0.25
28X
DETAIL M
PIN 1 INDEX
2.95
3.25
PIN 1
INDEX AREA
5
B
C
0.1
2X
2X
C
0.1
A
5
G
M
M
1.0
1.00
0.05
C
0.1
C
0.05
C
SEATING PLANE
5
DETAIL G
VIEW ROTATED 90 CLOCKWISE
(0.5)
(0.25)
0.8
0.75
0.00
(1.73)
(0.25)
0.065
32X
0.015
(45 )5
4
PREFERRED CORNER CONFIGURATION
DETAIL N
0.60
0.24
0.60
0.24
4
DETAIL N
CORNER CONFIGURATION OPTION
DETAIL T
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
DETAIL T
BACKSIDE PIN 1 INDEX OPTION
(90 )
5
2X
2X 0.39
0.31
0.1
0.0
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
1.6
0.475
0.425
1.5
BACKSIDE
PIN 1 INDEX
0.25
0.15
R
DETAIL S
DETAIL M
PREFERRED BACKSIDE PIN 1 INDEX
0.217
0.137
(0.25)
0.217
0.137
(0.1)
DETAIL S
PREFERRED BACKSIDE PIN 1 INDEX
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
5. COPLANARITY APPLIES TO LEADS, CORNER
LEADS, AND DIE ATTACH PAD.
6. FOR ANVIL SINGULATED QFN PACKAGES,
MAXIMUM DRAFT ANGLE IS 12.
Document Number: MC13191
Rev. 1.3
08/2005
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