Alpha is a trademark of Digital Equipment Corporation. Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM
Corporation.

www.fairchildsemi.com

Rev. 1.0.2

Features

· Drives Two N-Channel MOSFETs
· Operates from +5V Power Input
· Simple Single-Loop Control Design

- Voltage-Mode PWM Control

· Fast Transient Response

- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio

· Excellent Output Voltage Regulation
· TTL Compatible 5 Bit Digital-to-Analog Output Voltage

Selection
- Wide Range - 1.3V

to 3.5V

- 0.1V Binary Steps from 2.1V

to 3.5V

- 0.05V Binary Steps from 1.3V

to 2.1V

· Power-Good Output Voltage Monitor
· Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element, Uses

MOSFET's R

DS(ON)

· Small Converter Size

- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from

50kHz to 1MHz

Applications

· Power Supply for Pentium

, Pentium Pro, PowerPCTM

and AlphaTM Microprocessors

· High-Power 5V to 3.xV DC-DC Regulators
· Low-Voltage Distributed Power Supplies

Description

The RC5054A provides complete control and protection for
a DC-DC converter optimized for high-performance micro-
processor applications. It is designed to drive two N-Channel
MOSFETs in a synchronous-rectified buck topology. The
RC5054A integrates all of the control, output adjustment,
monitoring and protection functions into a single package.

The output voltage of the converter is easily adjusted and
precisely regulated. The RC5054A includes a 5-input digital-
to-analog converter (DAC) that adjusts the output voltage
from 2.1V

to 3.5V

in 0.1V increments and from

1.3V

to 2.1V

in 0.05V steps.

The RC5054A provides simple, single feedback loop, volt-

RC5054A

Programmable Synchronous DC-DC Converter
Controller for Low Voltage Microprocessors

Block Diagram

D/A

CONVERTER

(DAC)

OSCILLATOR

SOFT-

START

REFERENCE

POWER-ON

RESET (POR)

115%

110%

90%

INHIBIT

PWM

COMPARATOR

ERROR

AMP

VCC

PGOOD

PWM

OVP

GND

VSEN

OCSET

VID0
VID1
VID2
VID3

COMP

DACOUT

OVER-

VOLTAGE

OVER-

CURRENT

GATE

CONTROL

LOGIC

BOOT

UGATE

PHASE

200

VID4

LGATE

PGND

RC5054A

PRODUCT SPECIFICATION

age-mode control with fast transient response. It includes a
200KHz free-running triangle-wave oscillator that is adjust-
able from 50KHz to 1MHz. The error amplifier features a
15MHz gain-bandwidth product and 6V/

s slew rate which

enables high converter bandwidth for fast transient perfor-
mance. The resulting PWM duty ratio ranges from 0% to
100%.

The RC5054A monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within

10%. The RC5054A

protects against over-current conditions by inhibiting PWM
operation. Built-in over-voltage protection triggers an exter-
nal SCR to crowbar the input supply. The RC5054A moni-
tors the current by using the R

DS(ON)

of the upper MOSFET

which eliminates the need for a current sensing resistor.

Pin Assignments

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

LGATE

PGND

OVP

BOOT

UGATE

PHASE

PGOOD

GND

RC5054

(SOIC)

TOP VIEW

Pin Definitions

Pin Number Pin Names

Pin Function Description

VSEN

This pin is connected to the converter's output voltage. The PGOOD and OVP
comparator circuits use this signal to report output voltage status and for overvoltage
protection.

OCSET

Connect a resistor (R

OCSET

) from this pin to the drain of the upper MOSFET.

OCSET

, an internal 200

A current source (I

OCS

), and the upper MOSFET on-

resistance (R

DS(ON)

) set the converter over-current (OC) trip point according to the

following equation:

An over-current trip cycles the soft-start function.

Connect a capacitor from this pin to ground. This capacitor, along with an internal
10

A current source, sets the soft-start interval of the converter.

4-8

VID0-VID4

VID0-4 are the input pins to the 5-bit DAC. The states of these five pins program the
internal voltage reference (DACOUT). The level of DACOUT sets the converter
output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies
DACOUT for the 32 combinations of DAC inputs.

COMP

COMP and FB are the available external pins of the error amplifier. The FB pin is the
inverting input of the error amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control feedback loop of the
converter.

GND

Signal ground for the IC. All voltage levels are measured with respect to this pin.

PGOOD

PGOOD is an open collector output used to indicate the status of the converter
output voltage. This pin is pulled low when the converter output is not within

10% of

the DACOUT reference voltage.

PHASE

Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor
the voltage drop across the MOSFET for over-current protection. This pin also
provides the return path for the upper gate drive.

UGATE

Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the
upper MOSFET.

BOOT

This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may
be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET.

PGND

This is the power ground connection. Tie the lower MOSFET source to this pin.

PEAK

OCS

OCSET

DS ON

(

)

----------------------------------------

PRODUCT SPECIFICATION

RC5054A

Absolute Maximum Ratings

Recommended Operating Conditions

Thermal Characteristics

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

LGATE

Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the
lower MOSFET.

VCC

Provide a 12V bias supply for the chip to this pin.

OVP

The OVP pin can be used to drive an external SCR in the event of an overvoltage
condition.

This pin provides oscillator switching frequency adjustment. By placing a resistor
(R

) from this pin to GND, the nominal 200KHz switching frequency is increased

according to the following equation:

Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the
switching frequency according to the following equation:

Min.

Max.

Power Input Voltage, V

Supply Voltage, V

+13.5V

Boot Voltage, V

BOOT

- V

PHASE

+13.5V

or I/O Voltage

GND -0.3V

+ 0.3V

ESD Classification

Class 2

Min.

Max.

Supply Voltage, V

+12V -10%

+12V +10%

Ambient Temperature Range

C 70

Junction Temperature Range

C 125

Parameter

Conditions

Min.

Typ.

Max.

Units

Thermal Resistance

SOIC Package
SOIC Package

With 3in

of Copper

110

C/W

Maximum Junction Temperature

Plastic Package

150

Maximum Storage Temperature Range

-65

150

Maximum Lead Temperature

Soldering 10s

300

Pin Definitions

(continued)

Pin Number Pin Names

Pin Function Description

200kHz

3.5

KHz x Kohm

[

]

Kohm

[

]

------------------------------------------------------------

to GND

(

)

200kHz

KHz x Kohm

[

]

Kohm

[

]

--------------------------------------------------------

to 12V

(

)

RC5054A

PRODUCT SPECIFICATION

Electrical Specifications

(Recommended Operating Conditions unless otherwise specified)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

VCC Supply Current

Nominal Supply

UGATE and LGATE Open

Power-On Reset

Rising VCC Threshold

OCSET

= 4.5V

10.4

Falling VCC Threshold

OCSET

= 4.5V

8.8

Rising V

OCSET

Threshold

1.26

Oscillator

Free Running Frequency

RT = OPEN

185

200

215

KHz

OSC

Ramp Amplitude

RT = Open

1.9

P-P

Reference and DAC

Initial Voltage Setpoint

LOAD

= 0.8A, V

OUT

= 2.000V

OUT

= 1.550V

1.980
1.534

2.000
1.550

2.020
1.566

V
V

Error Amplifier

DC Gain

GBW

Gain-Bandwidth Product

MHz

Slew Rate

COMP = 10pF

Gate Drivers

UGATE

Upper Gate Source

BOOT

- V

PHASE

= 12V

350

500

UGATE

Upper Gate Sink

UGATE

- V

PHASE

= 1V

100

LGATE

Lower Gate Source

= 12V, V

LGATE

= 6V

300

450

LGATE

Lower Gate Sink

UGATE

- V

PHASE

= 1V

100

Protection

Over-Voltage Trip (V

SEN

/DACOUT)

115

120

OCSET

OCSET Current Source

OCSET

= 4.5V

170

200

230

OVP

OVP Sourcing Current

SEN

= 5.5V, V

OVP

= 0V

Soft Start Current

Power Good

Upper Threshold (V

SEN

/DACOUT)

VSEN Rising

106

111

Lower Threshold (V

SEN

/DACOUT)

VSEN Falling

Hysteresis (V

SEN

/DACOUT)

Upper and Lower Threshold

PGOOD

PGOOD Voltage Low

PGOOD

= -5mA

0.5

PRODUCT SPECIFICATION

RC5054A

Functional Description

Initialization

The RC5054A automatically initializes upon receipt of
power. Special sequencing of the input supplies is not neces-
sary. The Power-On Reset (POR) function continually moni-
tors the input supply voltages. The POR monitors the bias
volt-age at the V

pin and the input voltage (V

) on the

OCSET pin. The level on OCSET is equal to V

less a fixed

voltage drop (see over-current protection). The POR function
initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, V

and V

are equivalent and the

+12V power source must exceed the rising V

threshold

before POR initiates operation.

Soft Start

The POR function initiates the soft start sequence. An inter-
nal 10

A current source charges an external capacitor (C

)

on the SS pin to 4V. Soft start clamps the error amplifier out-
put (COMP pin) and reference input (+ terminal of error
amp) to the SS pin voltage. Figure 1 shows the soft start
interval with C

= 0.1

F. Initially the clamp on the error

amplifier (COMP pin) controls the converter's output volt-
age. At t

in Figure 1, the SS voltage reaches the valley of the

oscillator's triangle wave. The oscillator's triangular wave-
form is compared to the ramping error amplifier voltage. This
generates PHASE pulses of increasing width that charge the
output capacitor(s). This interval of increasing pulse width
continues to t

. With sufficient output voltage, the clamp on

the reference input controls the output voltage. This is the
interval between t

and t

in Figure 1. At t

the SS voltage

exceeds the DACOUT voltage and the output voltage is in
regulation. This method provides a rapid and controlled
output voltage rise. The PGOOD signal toggles `high' when
the output voltage (VSEN pin) is within

5% of DACOUT.

The 2% hysteresis built into the power good comparators
prevents PGOOD oscillation due to nominal output voltage
ripple.

Figure 1. Soft Start Interval

Time (5ms/DIV)

SOFT-START

(1V/DIV)

OUTPUT

(1V/DIV)

VOLTAGE

PGOOD

(2V/DIV)

Over-Current Protection

The over-current function protects the converter from a
shorted output by using the upper MOSFET's on-resistance,
R

DS(ON)

to monitor the current. This method enhances the

converter's efficiency and reduces cost by eliminating a current
sensing resistor. The over-current function cycles the soft-
start function in a hiccup mode to provide fault protection. A
resistor (R

OCSET

) programs the over-current trip level. An

internal 200

A current sink develops a voltage across R

OCSET

that is referenced to V

. When the voltage across the upper

MOSFET (also referenced to V

) exceeds the voltage across

OCSET

, the over-current function initiates a soft-start

sequence. The soft-start function discharges C

with a 10

current sink and inhibits PWM operation. The soft-start func-
tion recharges C

, and PWM operation resumes with the

error amplifier clamped to the SS voltage. Should an over-
load occur while recharging C

, the soft start function

inhibits PWM operation while fully charging C

to 4V to

complete its cycle. Figure 2 shows this operation with an
overload condition. Note that the inductor current increases
to over 15A during the CSS charging interval and causes an
over-current trip. The converter dissipates very little power
with this method. The measured input power for the condi-
tions of Figure 2 is 2.5W.

The over-current function will trip at a peak inductor current
(I

PEAK

) determined by:

Figure 2. Over-Current Operation

where I

OCSET

is the internal OCSET current source (200

typical). The OC trip point varies mainly due to the MOSFET's
R

DS(ON)

variations. To avoid over-current tripping in the

normal operating load range, find the R

OCSET

resistor from

the equation above with:

· The maximum R

DS(ON)

at the highest junction temperature.

· The minimum I

OCSET

from the specification table.

· Determine I

PEAK

for I

PEAK

> I

OUT(MAX)

+ (

I)/2,

where

I is the output inductor ripple current.

PEAK

OCSET

DS ON

(

)

--------------------------------------------

Output Inductor

Soft

-Start

Time (20ms/DIV)

10A

15A

RC5054A

PRODUCT SPECIFICATION

Table 1. Output Voltage Table

Note:
1. 0 = connected to GND or V

, 1 = OPEN

PIN NAME

NOMINAL

OUTPUT

VOLTAGE

PIN NAME

NOMINAL

OUTPUT

VOLTAGE

VID4

VID3

VID2

VID1

VID0

VID4

VID3

VID2

VID1

VID0

1.30

SHDN

1.35

2.1

1.40

2.2

1.45

2.3

1.50

2.4

1.55

2.5

1.60

2.6

1.65

2.7

1.70

2.8

1.75

2.9

1.80

3.0

1.85

3.1

1.90

3.2

1.95

3.3

2.00

3.4

2.05

3.5

For an equation for the ripple current see the section under
component guidelines titled `Output Inductor Selection.'

A small ceramic capacitor should be placed in parallel with
R

OCSET

to smooth the voltage across R

OCSET

in the pres-

ence of switching noise on the input voltage.

Output Voltage Program

The output voltage of a RC5054A converter is programmed
to discrete levels between 1.3V

and 3.5V

. The voltage

identification (VID) pins program an internal voltage refer-
ence (DACOUT) with a 5-bit digital-to-analog converter

(DAC). The level of DACOUT also sets the PGOOD and
OVP thresholds. Table 1 specifies the DACOUT voltage for
the 32 combinations of open or short connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exer-
cise the overvoltage protection.

Grounding any combination of the VID pins increases the
DACOUT voltage.

PRODUCT SPECIFICATION

RC5054A

Typical Application

+12V

OUT

PGND

RC5054

VSEN

COMP

VID0
VID1
VID2
VID3

PGOOD

D/A

GND

OSC

LGATE

UGATE

OCSET

PHASE

BOOT

VCC

= +5V

OVP

MONITOR AND

PROTECTION

VID4

Applications Discussion

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These intercon-
necting impedances should be minimized by using wide, short
printed circuit traces. The critical components should be
located as close together as possible, using ground plane
construction or single point grounding.

Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board The components shown in
Figure 3 should be located as close together as possible. Please
note that the capacitors C

and C

each represent numerous

physical capacitors. Locate the RC5054A within 3 inches of
the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs'
gate and source connections from the RC5054A must be
sized to handle up to 1A peak current.

Figure 3. Printed Circuit Board

Power and Ground Planes or Islands

Figure 4 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C

close to the SS pin because the internal current source is only
10

A. Provide local V

decoupling between V

and

GND pins. Locate the capacitor, C

BOOT

as close as practical

to the BOOT and PHASE pins.

Figure 4. Printed Circuit Board

Small Signal Layout Guidelines

Feedback Compensation

Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

OUT

) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (V

E/A

) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V

at the

PHASE node. The PWM wave is smoothed by the output
filter (L

and C

PGND

LGATE

UGATE

PHASE

OUT

RETURN

RC5054A

+12V

RC5054A

GND

VCC

BOOT

OUT

PHASE

BOOT

VCC

RC5054A

PRODUCT SPECIFICATION

Figure 5. Voltage-Mode Buck

Converter Compensation Design

The modulator transfer function is the small-signal transfer
function of V

OUT

E/A

. This function is dominated by a DC

Gain and the output filter (L

and C

), with a double pole

break freaquency at F

and a zero at F

ESR

. The DC Gain of

the modulator is simply the input voltage (V

) divided by

the peak-to-peak oscillator voltage

OSC

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
(internal to the RC5054A) and the impedance networks Z

and Z

. The goal of the compensation network is to provide

a closed loop transfer function with the highest 0dB crossing
frequency (f

0dB

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f

0dB

and

180 degrees. The equations below relate the compensation
network's poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:

Pick Gain (R2/R1) for desired converter bandwidth

Place 1

Zero Below Filter's Double Pole (~75% F

)

Place 2

Zero at Filter's Double Pole

Place 1

Pole at the ESR Zero

Place 2

Pole at Half the Switching Frequency

Check Gain against Error Amplifier's Open-Loop Gain

Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

Figure 6 shows an asymptotic plot of the DC-DC converter's
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F

with the capabili-

ties of the error amplifier. The Closed Loop Gain is con-
structed on the log-log graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer func-
tion to the compensation transfer function and plotting the
gain.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth (BW) over-

all loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

Figure 6. Asymptotic Bode Plot of Converter Gain

OUT

OSC

REFERENCE

ESR

OSC

ERROR
AMP

PWM

DRIVER

(PARASITIC)

DACOUT

COMP

OUT

RC5054

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

E/A

-------------------------------------

ESR

-------------------------------------

--------------------------------

---------------------

----------------------------------------------------

(

)

---------------------------------------------------

--------------------------------

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP
ERROR AMP GAIN

20LOG

ESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

OSC

)

MODULATOR

GAIN

(R2/R1)

CLOSED LOOP

GAIN

PRODUCT SPECIFICATION

RC5054A

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of capaci-
tors and careful layout.

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the tran-
sient and slow the current load rate seen by the bulk capaci-
tors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and volt-
age rating requirements rather than actual capacitance
requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance compo-
nents. Consult with the manufacturer of the load on specific
decoupling requirements. For example, Intel recommends
that the high frequency decoupling for the Pentium Pro be
composed of at least forty (40) 1

F ceramic capacitors in the

1206 surface-mount package.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor's ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the useful-
ness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor's imped-
ance with frequency to select a suitable component. In most
cases, multiple electrolytic capacitors of small case size per-
form better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter's response
time to the load transient. The inductor value determines the
converter's ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter's response time to a load transient.

One of the parameters limiting the converter's response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
RC5054A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor. Mini-
mizing the response time can minimize the output capaci-
tance required.

The response time to a transient is different for the applica-
tion of load and the removal of load. The following equations
give the approximate response time interval for application
and removal of a transient load:

where: I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application
or removal of load and dependent upon the DACOUT setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capaci-
tors for high frequency decoupling and bulk capacitors to
supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable oper-
ation, select the bulk capacitor with voltage and current ratings
above the maximum input voltage and largest RMS current
required by the circuit. The capacitor voltage rating should be
at least 1.25 times greater than the maximum input voltage
and a voltage rating of 1.5 times is a conservative guideline.
The RMS current rating requirement for the input capacitor
of a buck regulator is approximately 1/2 the DC load current.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MVGX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-cur-
rent at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.

OUT

------------------------------

OUT

--------------

OUT

ESR

RISE

TRAN

OUT

------------------------------

FALL

TRAN

OUT

--------------------------

RC5054A

PRODUCT SPECIFICATION

MOSFET Selection/Considerations

The RC5054A requires 2 N-Channel power MOSFETs.
These should be selected based upon R

DS(ON)

, gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipa-
tion, package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses
are the largest component of power dissipation for both the
upper and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor (see the
equations below). Only the upper MOSFET has switching
losses, since the Schottky rectifier clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not ade-
quately model power loss due the reverse-recovery of the
lower MOSFET's body diode. The gate-charge losses are
dissipated by the RC5054A and don't heat the MOSFETs.
However, large gate-charge increases the switching interval,
t

, which increases the upper MOSFET switching losses.

Ensure that both MOSFETs are within their maximum junc-
tion temperature at high ambient temperature by calculating
the temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary depend-
ing upon MOSFET power, package type, ambient tempera-
ture and air flow.

Where: D is the duty cycle = V

OUT

is the switching interval, and

is the switching frequency

Standard-gate MOSFETs are normally recommended for
use with the RC5054A. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET's absolute gate-
to-source voltage rating determine whether logic-level
MOSFETs are appropriate.

Figure 7 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V

. The boot capacitor, C

BOOT

develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V

less the boot diode drop (V

) when the lower MOSFET,

Q2 turns on. Logic-level MOSFETs can only be used if the
MOSFET's absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V

Figure 7. Upper Gate Drive - Bootstrap Option

Figure 8 shows the upper gate drive supplied by a direct con-
nection to V

. This option should only be used in converter

systems where the main input voltage is +5V

or less. The

peak upper gate-to-source voltage is approximately V

less

the input supply. For +5V main power and +12VDC for the
bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage
rating exceeds the maximum voltage applied to V

Figure 8. Upper Gate Drive - Direct V

Drive Option

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.

UPPER

DS ON

(

)

1
3

---Io

LOWER

DS ON

(

)

(

)

+12V

+5V

PGND

RC5054A

GND

LGATE

UGATE

PHASE

BOOT

VCC

NOTE:

NOTE:
V

G-S

BOOT

G-S

-V

+12V

PGND

RC5054A

GND

LGATE

UGATE

PHASE

BOOT

+5V OR LESS

NOTE:

NOTE:
V

G-S

-5V

RC5054A

PRODUCT SPECIFICATION

8/11/99 0.0m 004

Stock#DS30005054

1998 Fairchild Semiconductor Corporation

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Ordering Information

Part Number

Temperature Range (

C) Package

RC5054AM

0 to 70

20 Ld SOIC

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: RC5054A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: RC5054A