2005 Fairchild Semiconductor Corporation
FDP8880 / FDB8880 Rev. A
February 2005
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FD
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1
FDP8880 / FDB8880
N-Channel PowerTrench
MOSFET
30V, 54A, 11.6m
Features
r
DS(ON)
= 14.5m
, V
GS
= 4.5V, I
D
= 40A
r
DS(ON)
= 11.6m
, V
GS
= 10V, I
D
= 40A
High performance trench technology for extremely low
r
DS(ON)
Low gate charge
High power and current handling capability
Applications
DC/DC converters
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r
DS(ON)
and fast switching speed.
TO-263AB
FDB SERIES
GATE
SOURCE
DRAIN
(FLANGE)
TO-220AB
FDP SERIES
D
G
S
DRAIN
DRAIN
GATE
SOURCE
(FLANGE)
2005 Fairchild Semiconductor Corporation
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MOSFET Maximum Ratings
T
C
= 25C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Electrical Characteristics
T
C
= 25C unless otherwise noted
Off Characteristics
On Characteristics
Symbol
Parameter
Ratings
Units
V
DSS
Drain to Source Voltage
30
V
V
GS
Gate to Source Voltage
20
V
I
D
Drain Current
54
A
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 25
o
C, V
GS
= 4.5V)
48
A
Continuous (T
amb
= 25
o
C, V
GS
= 10V, with R
JA
= 43
o
C/W)
11
A
Pulsed
Figure 4
A
E
AS
Single Pulse Avalanche Energy (Note 1)
31
mJ
P
D
Power dissipation
55
W
Derate above 25
o
C
0.37
W/
o
C
T
J
, T
STG
Operating and Storage Temperature
-55 to 175
o
C
R
JC
Thermal Resistance Junction to Case TO-220,TO-263
2.73
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-220,TO-262 ( Note 2)
62
o
C/W
R
JA
Thermal Resistance Junction to Ambient TO-263, 1in
2
copper pad area
43
o
C/W
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDP8880
FDP8880
TO-220AB
Tube
N/A
50 units
FDB8880
FDB8880
TO-263AB
330mm
24mm
800 units
FDP8880
FDP8880_NL (Note 3)
TO-220AB
Tube
N/A
50 units
FDB8880
FDB8880_NL (Note 3)
TO-263AB
330mm
24mm
800 units
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0V
30
-
-
V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24V
-
-
1
A
V
GS
= 0V
T
C
= 150
o
C
-
-
250
I
GSS
Gate to Source Leakage Current
V
GS
=
20V
-
-
100
nA
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
A
1.2
-
2.5
V
r
DS(ON)
Drain to Source On Resistance
I
D
= 40A, V
GS
= 10V
-
0.0095 0.0116
I
D
= 40A, V
GS
= 4.5V
-
0.012
0.0145
I
D
= 40A, V
GS
= 10V,
T
J
= 175
o
C
-
0.015
0.019
2005 Fairchild Semiconductor Corporation
FDP8880 / FDB8880 Rev. A
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Dynamic Characteristics
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1: Starting T
J
= 25C, L = 34uH, I
AS
= 43A,Vdd = 27V, Vgs = 10V.
2: Pulse width = 100s.
3: FDP8880_NL / FDB8880_NL is lead free product.
FDP8880_NL / FDB8880_NL marking will appear on the reel label.
C
ISS
Input Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
-
1240
-
pF
C
OSS
Output Capacitance
-
255
-
pF
C
RSS
Reverse Transfer Capacitance
-
147
-
pF
R
G
Gate Resistance
V
GS
= 0.5V, f = 1MHz
-
2.7
-
Q
g(TOT)
Total Gate Charge at 10V
V
GS
= 0V to 10V
V
DD
= 15V
I
D
= 40A
I
g
= 1.0mA
-
22
29
nC
Q
g(5)
Total Gate Charge at 5V
V
GS
= 0V to 5V
-
12
16
nC
Q
g(TH)
Threshold Gate Charge
V
GS
= 0V to 1V
-
1.6
2.1
nC
Q
gs
Gate to Source Gate Charge
-
3.2
-
nC
Q
gs2
Gate Charge Threshold to Plateau
-
2.0
-
nC
Q
gd
Gate to Drain "Miller" Charge
-
4.8
-
nC
t
ON
Turn-On Time
V
DD
= 15V, I
D
= 40A
V
GS
= 10V, R
GS
= 13.6
-
-
171
ns
t
d(ON)
Turn-On Delay Time
-
8
-
ns
t
r
Rise Time
-
107
-
ns
t
d(OFF)
Turn-Off Delay Time
-
47
-
ns
t
f
Fall Time
-
51
-
ns
t
OFF
Turn-Off Time
-
-
147
ns
V
SD
Source to Drain Diode Voltage
I
SD
= 40A
-
-
1.25
V
I
SD
= 3.5A
-
-
1.0
V
t
rr
Reverse Recovery Time
I
SD
= 40A, dI
SD
/dt = 100A/
s
-
-
27
ns
Q
RR
Reverse Recovered Charge
I
SD
= 40A, dI
SD
/dt = 100A/
s
-
-
18
nC
2005 Fairchild Semiconductor Corporation
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Typical Characteristics
T
C
= 25C unless otherwise noted
Figure 1. Normalized Power Dissipation vs Case
Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
T
C
, CASE TEMPERATURE (
o
C)
PO
WE
R
D
I
SSI
P
A
T
I
O
N
M
U
L
T
I
P
L
I
ER
0
0
25
50
75
100
175
0.2
0.4
0.6
0.8
1.0
1.2
125
150
I
D
, DRAIN CURRE
NT
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
0
20
40
60
25
50
75
100
125
150
175
0.1
1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.01
2
t, RECTANGULAR PULSE DURATION (s)
Z
JC
, NO
RM
AL
IZ
E
D
T
H
E
R
M
A
L
IM
P
E
D
ANCE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
600
50
I
DM
, P
E
AK CURRE
NT
(
A
)
t, PULSE WIDTH (s)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
GS
= 4.5V
V
GS
= 10V
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Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics
T
C
= 25C unless otherwise noted
0.1
1
10
100
400
1
10
40
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
,
D
RAIN CURRE
NT
(
A
)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
10
s
1ms
DC
100
s
10ms
1
10
100
0.001
0.01
0.1
1
500
100
I
AS
, A
V
AL
ANCHE
CURRE
NT
(
A
)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
10
0
20
40
60
80
1.5
2.0
2.5
3.0
3.5
I
D
, DRAIN CUR
RE
NT
(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= -55
o
C
T
J
= 25
o
C
4.0
0
40
80
120
160
0
0.25
0.5
0.75
1.0
I
D
, DRA
I
N
CU
RRE
NT
(
A
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 10V
V
GS
= 3.5V
V
GS
= 3V
V
GS
= 4.5V
V
GS
= 2.5V
8
12
16
20
2
4
6
8
10
I
D
= 5A
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 54A
r
DS(
O
N)
,
D
RAIN T
O
S
O
URCE
O
N
R
E
S
I
S
T
ANCE
(
m
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0.7
0.85
1.02
1.19
1.36
1.53
-80
-40
0
40
80
120
160
200
NO
RM
A
L
IZ
E
D
DRAIN T
O
S
O
U
RCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
V
GS
= 10V, I
D
= 54A
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
1.7
2005 Fairchild Semiconductor Corporation
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Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
Typical Characteristics
T
C
= 25C unless otherwise noted
0.3
0.6
0.9
1.2
1.5
-80
-40
0
40
80
120
160
200
V
GS
= V
DS
, I
D
= 250
A
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
0.9
1.0
1.1
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URC
E
I
D
= 250
A
BRE
AKDO
W
N
V
O
L
T
A
G
E
1000
2000
0.1
1
10
30
100
C, CAP
A
C
IT
ANCE
(
p
F
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
0
2
4
6
8
10
0
5
10
15
20
25
V
GS
,
G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
Q
g
, GATE CHARGE (nC)
V
DD
= 15V
I
D
= 54A
I
D
= 5A
WAVEFORMS IN
DESCENDING ORDER:
2005 Fairchild Semiconductor Corporation
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Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 1V
Q
gs2
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
Q
g(5)
V
GS
= 5V
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
2005 Fairchild Semiconductor Corporation
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PSPICE Electrical Model
.SUBCKT FDP8880 2 1 3 ; rev October 2004
Ca 12 8 9.5e-10
Cb 15 14 9.5e-10
Cin 6 8 1.15e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 32.88
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.3e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.7e-9
RLgate 1 9 53
RLdrain 2 5 10
RLsource 3 7 17
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.0e-3
Rgate 9 20 2.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.8e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}
.MODEL DbodyMOD D (IS=3E-12 IKF=10 N=1.01 RS=5e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=4.8e-10 M=0.55 TT=1e-11 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.8e-6)
.MODEL DplcapMOD D (CJO=5.5e-10 IS=1e-30 N=10 M=0.45)
.MODEL MstroMOD NMOS (VTO=2.10 KP=170 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.75 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.2)
.MODEL MweakMOD NMOS (VTO=1.39 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.0e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=-12e-3 TC2=.35e-4)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6)
.MODEL RvtempMOD RES (TC1=-2.78e-3 TC2=1.5e-6)
.MODEL RvthresMOD RES (TC1=-1e-3 TC2=-8.2e-6)
MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.3 VOFF=-0.8)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=-1.3)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2005 Fairchild Semiconductor Corporation
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SABER Electrical Model
rev October 2004
template FDP8880 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=3e-12,ikf=10,nl=1.01,rs=5e-3,trs1=8e-4,trs2=2e-7,cjo=4.8e-10,m=0.55,tt=1e-11,xti=2)
dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.8e-6)
dp..model dplcapmod = (cjo=5.5e-10,isl=10e-30,nl=10,m=0.45)
m..model mstrongmod = (type=_n,vto=2.10,kp=170,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=1.75,kp=10,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.39,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.3,voff=-0.8)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.8,voff=-1.3)
c.ca n12 n8 = 9.5e-10
c.cb n15 n14 = 9.5e-10
c.cin n6 n8 = 1.15e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 32.88
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.3e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.7e-9
res.rlgate n1 n9 = 53
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 17
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=8.0e-4,tc2=-8e-7
res.rdrain n50 n16 = 1.0e-3, tc1=-12e-3,tc2=.35e-4
res.rgate n9 n20 = 2.2
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.8e-3, tc1=5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1e-3,tc2=-8.2e-6
res.rvtemp n18 n19 = 1, tc1=-2.78e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
2005 Fairchild Semiconductor Corporation
FDP8880 / FDB8880 Rev. A
www.fairchildsemicom
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PSPICE Thermal Model
REV 23 December 2003
FDP8880T
CTHERM1 TH 6 8e-4
CTHERM2 6 5 1e-3
CTHERM3 5 4 2.5e-3
CTHERM4 4 3 2.6e-3
CTHERM5 3 2 8e-3
CTHERM6 2 TL 1.5e-2
RTHERM1 TH 6 1.44e-1
RTHERM2 6 5 1.9e-1
RTHERM3 5 4 3.0e-1
RTHERM4 4 3 4.0e-1
RTHERM5 3 2 5.7e-1
RTHERM6 2 TL 5.8e-1
SABER Thermal Model
SABER thermal model FDP8880T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =8e-4
ctherm.ctherm2 6 5 =1e-3
ctherm.ctherm3 5 4 =2.5e-3
ctherm.ctherm4 4 3 =2.6e-3
ctherm.ctherm5 3 2 =8e-3
ctherm.ctherm6 2 tl =1.5e-2
rtherm.rtherm1 th 6 =1.44e-1
rtherm.rtherm2 6 5 =1.9e-1
rtherm.rtherm3 5 4 =3.0e-1
rtherm.rtherm4 4 3 =4.0e-1
rtherm.rtherm5 3 2 =5.7e-1
rtherm.rtherm6 2 tl =5.8e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
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Definition of Terms
ACExTM
ActiveArrayTM
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CROSSVOLTTM
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EcoSPARKTM
E
2
CMOSTM
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Definition
Advance Information
Formative or In
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This datasheet contains the design specifications for
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supplementary data will be published at a later date.
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changes at any time without notice in order to improve
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This datasheet contains final specifications. Fairchild
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This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
FDP8880 / FDB8880 Rev. A
www.fairchildsemi.com
11
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