August 1998
Revised January 1999
FC94
0L Lo
w V
o
l
t
a
ge 1
to
18
Cloc
k
Dist
ri
b
u
ti
on De
vice
wit
h
Select
ab
le
PECL o
r
L
V
TTL I
nput
1999 Fairchild Semiconductor Corporation
DS500140.prf
www.fairchildsemi.com
FC940L
Low Voltage 1 to 18 Clock Distribution Device with
Selectable PECL or LVTTL Input
General Description
The FC940L is a 1 to 18 low voltage clock fanout buffer.
The device allows for the selection of either differential
PECL or LVTTL/CMOS input levels. The 18 outputs are
compatible with LVCMOS or LVTTL technology and are
capable of driving 50
series or parallel terminated lines.
The device has a minimal propagation delay and features
low part-to-part and pin-to-pin skews. The outputs of the
device are designed to operate at either 2.5V or 3.3V V
CC
.
The output transistors have a 20
(30
) impedance at
3.3V (2.5V) V
CC
. The input and core circuitry operate at
3.3V.
The FC940L is fabricated in a high performance BiCMOS
Process.
Features
s
Selectable Differential PECL or LVTTL/CMOS inputs
s
2.5V/3.3V output V
CC
supply operation
s
Typical propagation delays 2.5 ns
s
Part-to-Part skew
<
900 ps
s
Typical Pin-to-Pin skew 200 ps
s
Ability to drive 50
series or parallel terminated trans-
mission lines
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Pin compatible to MPC940L
s
32 pin TQFP package
Ordering Code:
Device also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for TQFP
Pin Descriptions
Truth Table
H
=
High Voltage Level
L
=
Low Voltage Level
X
=
Immaterial
Order Number
Package Number
Package Description
FC940LVB
VBE32A
32-Lead Thin Quad Flat Package, JEDEC MO-136, 7mm Square
Pin Names
Description
PECL_CLK, PECL_CLK
Differential PECL Input
LVC_CLK
LVTTL/CMOS Clock Input
SEL
Input Selection Pin
O[0:17]
Low Voltage CMOS Outputs
Inputs
Outputs
PECL_CLK
LVC_CLK
SEL
O
0
O
17
L
X
L
L
H
X
L
H
X
L
H
L
X
H
H
H
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2
FC940
L
Functional Description
The FC940L is a 1 to 18 Clock distribution fanout buffer.
The devices accept either a differential PECL or LVCMOS/
LVTTL input signal and generates 18 LVCMOS output sig-
nals. The SEL signal selects the differential PECL CLK
input signals when held at a logic "L" and selects the LVC-
MOS CLK input signal when held at a logic "H". The com-
plete functional operation is shown in the Truth Table.
The output buffers support the ability to be powered by
either a 2.5V or 3.3V V
CC
. The internal core voltage is
required to be a 3.3V.
The selectable input stage allows the device to be used in
combination with either LVTTL/LVCMOS or LVPECL clock
generation devices. The LVPECL inputs make this device
ideal for use in large clock distribution systems where there
are multiple levels of hierarchy.
Logic Diagram
3
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FC94
0L
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 2: Absolute Maximum Rating must be observed.
Note 3: V
CC
O
V
CC
1
DC Electrical Characteristics (V
CC
I
=
3.3
0.165V, V
CC
O
=
3.3
0.165V)
Note 4: VCMR is the difference between V
CC
I and the most positive side of the differential Input signal. Normal operation is obtained when the "high" input is
within the VCMR Range and the inputs swing lies within the V
PP
specification. See figure 6.
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to
+
4.6V
Output Voltage (V
O
) (Note 2)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
V
O
>
V
CC
+
50 mA
DC Output Source/Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current per Supply Pin
(I
CC
or Ground)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Ambient Temperature Under Bias (T
A
)
0
C to
+
70
C
Case Temperature Under Bias (T
C
)
0
C to
+
110
C
Power Supply Voltage (V
CC
)
V
CC
I
3.135V to 3.465V
V
CC
O(Note 3)
2.375 to 3.465V
Input Voltage (V
IN
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Output Current in I
OH
/I
OL
V
CC
O
=
3.135V to 3.465V
24 mA
V
CC
O
=
2.375V to 2.625V
16 mA
Free Air Operating Temperature
0
C to
+
70
C
Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.135V
<
10 ns/V
Symbol
Parameter
Conditions
V
CC
I
V
CC
O
T
A
=
0
C to
+
70
C
Units
Min
Max
V
IH
High Level Input Voltage
PECLK_CLK
3.1353.465 3.1353.465
2.135
2.42
V
OTHER
3.1353.465 3.1353.465
2.00
V
V
IL
Low Level Input Voltage
PECLK_CLK
3.1353.465 3.1353.465
1.49
1.825
V
OTHER
3.1353.465 3.1353.465
0.8
V
V
PP
Peak-to-Peak
Input Voltage
PECL_CLK
3.1353.465 3.1353.465
300
1000
mV
VCMR
Common Mode Range (Note 4)
3.1353.465 3.1353.465
V
CC
-
1.6
V
CC
-
0.8
V
V
OH
High Level Output Voltage
I
OH
=
-
100
A
3.1353.465 3.1353.465
V
CC
-
0.2
V
I
OH
=
-
24 mA
3.135
3.135
2.5
V
V
OL
Low Level Output Voltage
I
OL
=
100
A
3.1353.465 3.465
0.2
V
I
OL
=
24 mA
3.135
3.135
0.5
V
I
IN
Input Current
PECL_CLK
3.1353.465 3.1353.465
100
A
LVC_CLK
3.1353.465 3.1353.465
100
A
I
CC
Quiescent Supply Current
(I
CCI
+
I
CCO
)
All Outputs Low
(I
CCL
)
3.465
3.465
240
mA
All Outputs High
(I
CCH
)
3.465
3.465
225
mA
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4
FC940
L
DC Electrical Characteristics (V
CC
I
=
3.3V
0.165V, V
CC
O
=
2.5V
0.125V)
AC Electrical Characteristics (V
CC
I = 3.3V
0.165V, T
A
= 0
C to +70
C)
(Note 5)
Note 5: AC Specifications are measured into a 50
Parallel terminated line. See Figure 1. Measurements are made with an input rise time of 1 ns/V.
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay between any two outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH t
OSLH
).
Note 7: Part-to-Part Skew is defined as the variation in propagation delay between a specific output of device A and the same output of device B at the same
V
CC
, temperature, output loading and input signal conditions. This specification is valid where all outputs of the device are tied together. This specification is
guaranteed by design and statistical process distribution.
Note 8: This specification assumes an input waveform with 50% duty cycle. The worst case duty cycle degradation will typically occur at f
MAX
.
Capacitance
Symbol
Parameter
Conditions
V
CC
I
V
CC
O
T
A
=
0
C to
+
70
C
Units
Min
Max
V
IH
High Level Input Voltage
PECLK_CLK
3.1353.465 2.3752.625
2.135
2.42
V
OTHER
3.1353.465 2.3752.625
2.0
V
V
IL
Low Level Input Voltage
PECLK_CLK
3.1353.465 2.3752.625
1.49
1.825
V
OTHER
3.1353.465 2.3752.625
0.8
V
V
PP
Peak-to-Peak Input Voltage
3.1353.465 2.3752.625
300
1000
mV
VCMR
Common Mode Range (Note 4)
3.1353.465 2.3752.625
V
CC
-
1.6
V
CC
-
0.8
V
V
OH
High Level Output Voltage
I
OH
=
-
100
A
3.1353.405 2.3752.625
V
CC
-
0.2
V
I
OH
=
-
16 mA
3.135
2.375
1.7
V
V
OL
Low Level Output Voltage
I
OL
=
100
A
3.1353.465 2.3752.625
0.2
V
I
OL
=
16 mA
3.135
2.375
0.5
V
I
IN
Input Current
PECL_CLK
3.1353.465 2.3752.625
100
A
LVC_CLK
3.1353.465 2.3752.625
100
A
I
CC
Quiescent Supply Current
(I
CCI
+
I
CCO
)
All Outputs Low
(I
CCL
)
3.465
2.625
240
mA
All Outputs High
(I
CCH
)
3.465
2.625
225
mA
Symbol
Parameter
V
CC
O
=
3.3V
0.165V
V
CC
O
=
2.5V
0.125V
Units
Min
Typ
Max
Min
Typ
Max
f
max
Clock Frequency
150
150
MHz
t
PHL
Propagation Delay
t
PLH
PECL_CLK to O
n
2.5
3.5
2.5
3.7
ns
LVC_CLK to O
n
2.9
3.8
2.9
4.0
t
PHL
Propagation Delay
5.3
5.5
ns
t
PLH
SEL to O
n
t
r
Rise and Fall Time
t
f
V
CC
O
=
3.3V (0.8V to 2V)
600
ps
V
CC
O
=
2.5V (0.7V to 1.6V)
600
t
OSLH
Pin-to-Pin Output Skew
200
200
ps
t
OSHL
(Note 6)
t
SK(PR)
Part-to-Part Skew (Note 7)
900
900
ps
t
pwo
Output Pulse Width (Note 8)
45
55
45
55
%
Symbol
Parameter
Conditions
T
A
=
+
25
C
Typical
Units
C
IN
Input Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
4
pF
C
PD
Power Dissipation Capacitance
V
I
=
0V or V
CC
, f
=
10 MHz, V
CC
=
3.3V
8
pF
5
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FC94
0L
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Non-Inverting Output Signal
FIGURE 3. Waveform for Pin-to-Pin Output Skew
FIGURE 4. Duty Cycle Distortion
dpwh
=
(t
pwho
-t
pwhi
); dpwl
=
(t
pwlo
-t
pwli)
FIGURE 5. Output Pulse Width High/Low
FIGURE 6. Differential Input Signals
Symbol
V
MI
V
MO
VCCI
==
3.3V
0.165V
V
CC
O
=
3.3V
0.165V
V
CC
O
=
2.5V
0.125V
PECL_CLK
50% of Swing
1.5V
V
CC
/2
LVC_CLK
1.5V
1.5V
VCC/2
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