1999 Fairchild Semiconductor Corporation
DS010195
www.fairchildsemi.com
February 1989
Revised August 1999
7
4F899 9-Bi
t Latcha
ble T
r
ans
ceiver
74F899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The 74F899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. It has a guaranteed current
sinking capability of 24 mA at the A-bus and 64 mA at the
B-bus.
The 74F899 features independent latch enables for the
A-to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Features
s
Latchable transceiver with output sink of 24 mA at the
A-bus and 64 mA at the B-bus
s
Option to select generate parity and check or
"feed-through" data/parity in directions A-to-B or B-to-A
s
Independent latch enables for A-to-B and B-to-A
directions
s
Select pin for ODD/EVEN parity
s
ERRA and ERRB output pins for parity checking
s
Ability to simultaneously generate and check parity
s
May be used in systems applications in place of the
74F543 and 74F280
s
May be used in system applications in place of the
74F657 and 74F373 (no need to change T/R to check
parity)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignment for SOIC
Pin Assignment for PCC
Logic Symbol
Order Number
Package Number
Package Description
74F899SC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F899QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
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2
74F899
Input Loading/Fan-Out
Pin Descriptions
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
HIGH/LOW
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A
0
A
7
Data Inputs/
1.0/1.0
20
A/
-
0.6 mA
Data Outputs
150/40
-
3 mA/24 mA
B
0
B
7
Data Inputs/
1.0/1.0
20
A/
-
0.6 mA
Data Outputs
600/106.6
-
12 mA/64 mA
APAR
A Bus Parity
1.0/1.0
20
A/
-
0.6 mA
Input/Output
150/40
-
3 mA/24 mA
BPAR
B Bus Parity
1.0/1.0
20
A/
-
0.6 mA
Input/Output
600/106.6
-
12 mA/64 mA
ODD/EVEN
Parity Select Input
1.0/1.0
20
A/
-
0.6 mA
GBA, GAB
Output Enable Inputs
1.0/1.0
20
A/
-
0.6 mA
SEL
Mode Select Input
1.0/1.0
20
A/
-
0.6 mA
LEA, LEB
Latch Enable Inputs
1.0/1.0
20
A/
-
0.6 mA
ERRA, ERRB
Error Signal Outputs
50/33.3
-
1 mA/20 mA
Pin Names
Description
A
0
A
7
A Bus Data Inputs/Data Outputs
B
0
B
7
B Bus Data Inputs/Data Outputs
APAR, BPAR
A and B Bus Parity Inputs
ODD/EVEN
ODD/EVEN Parity Select, Active LOW for EVEN Parity
GBA, GAB
Output Enables for A or B Bus, Active LOW
SEL
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
LEA, LEB
Latch Enables for A and B Latches, HIGH for Transparent Mode
ERRA, ERRB
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
3
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7
4F899
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Note 1: O/E
=
ODD/EVEN
Functional Block Diagram
Inputs
Operation
GAB
GBA
SEL LEA LEB
H
H
X
X
X
Busses A and B are 3-STATE.
H
L
L
L
H
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity
APAR. Generated
parity checked against BPAR and output as ERRB. Generated parity also fed back
through the A latch for generate/check as ERRA.
H
L
L
X
L
Generates parity from B latch data based on O/E. Generated parity
APAR.
Generated parity checked against latched BPAR and output as ERRB.
H
L
H
X
H
BPAR/B[0:7]
APAR/A0:7] Feed-through mode. Generated parity checked against
BPAR and output as ERRB.
H
L
H
H
H
BPAR/B[0:7]
APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
L
H
L
H
L
Generates parity for A[0:7] based on O/E. Generated parity
BPAR. Generated parity
checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[0:7] based on O/E. Generated parity
BPAR. Generated
parity checked against APAR and output as ERRA. Generated parity also fed back
through the B latch for generate/check as ERRB.
L
H
L
L
X
Generates parity from A latch data based on O/E. Generated parity
BPAR.
Generated parity checked against latched APAR and output as ERRA.
L
H
H
H
L
APAR/A[0:7]
BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
L
H
H
H
H
APAR/A[0:7]
BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
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4
74F899
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
Twice the Rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a
HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a
LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
10% V
CC
2.0
V
I
OH
=
-
15 mA (B
n
, BPAR)
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
I
OL
=
20 mA
Voltage
(A
n
, APAR, ERRA, ERRB)
5% V
CC
0.55
V
I
OL
=
24 mA
(A
n
, APAR, ERRA, ERRB)
10% V
CC
0.55
I
OL
=
64 mA (B
n
, BPAR)
V
TH
Input Threshold Voltage
1.45
V
0.1V, Sweep Edge Rate must be
>
1V/50 ns
V
OLV
Negative Ground Bounce
1.0
V
Observed on "quiet" output during
Voltage
simultaneous switching of remaining outputs
V
OLP
Positive Ground Bounce
1.0
V
Observed on "quiet" output during
Voltage
simultaneous switching of remaining outputs
I
IL
Input Low Current
-
0.6
mA
Max V
IN
=
0.5V
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
(ODD/EVEN, GBA, GAB, SEL, LEA, LEB)
I
BVIT
Input HIGH Current
0.5
mA
Max
V
IN
=
5.5V
Breakdown (I/O)
(A
n
, B
n
, A
PAR
, B
PAR
)
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input Low Current
-
0.6
mA
Max
V
IN
=
0.5V
I
IH
+
Output Leakage Current
70
A
Max
V
I/O
=
2.7V
I
OZH
Current
(A
n
, B
n
, APAR, BPAR)
5
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7
4F899
DC Electrical Characteristics
(Continued)
AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
I
IL
+
Output Leakage
-
650
A
Max
V
I/O
=
0.5V
I
OZL
Current
(A
n
, B
n
, APAR, BPAR)
I
OS
Output Short-Circuit Current
-
60
-
150
Max
V
OUT
=
0V
mA
(A
n
, APAR, ERRA, ERRB)
-
100
-
225
Max
V
OUT
=
0V (B
n
, BPAR)
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCH
Power Supply Current
132
155
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
178
210
mA
Max
V
O
=
LOW, GAB
=
LOW,
GBA
=
HIGH, V
IL
=
LOW
I
CCZ
Power Supply Current
160
190
mA
Max
V
O
=
HIGH Z
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
Figure
Number
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
4.0
7.5
13.0
4.0
14.0
ns
Figure 1
t
PHL
A
n
, APAR to B
n
, BPAR
4.0
8.5
13.0
4.0
14.0
t
PLH
Propagation Delay
7.5
12.0
17.0
7.5
18.0
ns
Figure 2
t
PHL
A
n
, B
n
to BPAR, APAR
7.5
12.5
17.0
7.5
18.0
t
PLH
Propagation Delay
7.5
12.0
17.0
7.5
18.0
ns
Figure 3
t
PHL
A
n
, B
n
to ERRA, ERRB
7.5
12.5
17.0
7.5
18.0
t
PLH
Propagation Delay
4.5
7.5
11.0
4.5
12.0
ns
Figure 4
t
PHL
ODD/EVEN to ERRA, ERRB
4.5
8.0
11.0
4.5
12.0
t
PLH
Propagation Delay
4.5
7.5
11.5
4.5
12.5
ns
Figure 5
t
PHL
ODD/EVEN to APAR, BPAR
4.5
8.5
11.5
4.5
12.5
t
PLH
Propagation Delay
5.5
9.0
13.0
5.5
14.0
ns
Figure 6
t
PHL
APAR, BPAR to ERRA, ERRB
5.5
9.5
13.0
5.5
14.0
t
PLH
LEA/LEB to
9.5
13.0
17.5
7.5
18.0
ns
Figure 7
t
PHL
ERRA /ERRB
9.7
17.5
7.5
18.0
t
PLH
Propagation Delay
3.0
6.0
10.0
3.0
11.0
ns
Figure 10
t
PHL
SEL to APAR, BPAR
3.0
7.0
10.0
3.0
11.0
t
PLH
Propagation Delay
3.5
7.0
10.0
3.5
11.0
ns
Figure 11
t
PHL
LEB to A
n
, APAR
3.5
8.0
10.0
3.5
11.0
t
PLH
t
PHL
Propagation Delay
3.5
6.5
10.0
3.5
11.0
ns
Figure 11
LEA to B
n
, BPAR
3.5
7.5
10.0
3.5
11.0
t
PZH
Output Enable Time
1.0
4.5
10.0
1.0
11.0
ns
Figure 8,
Figure 9
t
PZL
GBA or GAB to A
n
,
1.0
6.5
10.0
1.0
11.0
APAR or B
n
, BPAR
t
PHZ
Output Disable Time
1.0
4.0
7.0
1.0
8.0
ns
Figure 8,
Figure 9
t
PLZ
GBA or GAB to A
n
,
1.0
4.0
7.0
1.0
8.0
APAR or B
n
, BPAR
t
S
(H)
Setup Time, HIGH or LOW
5.0
1.6
5.0
ns
Figure 12,
Figure 13
t
S
(L)
A
n
, B
n
to LEA, LEB
5.0
1.8
5.0
t
H
(H)
Hold Time, HIGH or LOW
0
-
1.7
0
ns
Figure 12,
Figure 13
t
H
(L)
A
n
, B
n
to LEA, LEB
0
-
1.5
0
t
W
Pulse Width for LEA, LEB
6.0
2.0
6.0
ns
Figure 14
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