June 1988
Revised October 1998
7
4
A
C
T323 8-
B
i
t
Uni
ver
sal Shif
t/
Stor
a
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e
gist
er wit
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Sync
hr
onous R
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set and C
o
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I
/
O Pins
1999 Fairchild Semiconductor Corporation
DS009787.prf
www.fairchildsemi.com
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
The ACT323 is an 8-bit universal shift/storage register with
3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q
0
and Q
7
to allow
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load and
store
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP
Pin Descriptions
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACT323PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Name
Description
CP
Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S
0
, S
1
Mode Select Inputs
SR
Synchronous Reset Input
OE
1
, OE
2
3-STATE Output Enable Inputs
I/O
0
I/O
7
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
Q
0
, Q
7
Serial Outputs
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2
74A
CT323
Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S
1
as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Inputs
Response
SR
S
1
S
0
CP
L
X
X
Synchronous Reset; Q
0
Q
7
=
LOW
H
H
H
Parallel Load; I/O
n
Q
n
H
L
H
Shift Right; DS
0
Q
0
, Q
0
Q
1
, etc.
H
H
L
Shift Left; DS
7
Q
7
, Q
7
Q
6
, etc.
H
L
L
X
Hold
3
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7
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T323
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74A
CT323
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Input Voltage (V
I
)
-
0.5V to V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source or
Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Junction Temperature (T
J
)
PDIP
140
C
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
=
+
25
C T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum High Level
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum Low Level
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum High Level
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 2)
V
OL
Maximum Low Level
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
-
24 mA
5.5
0.36
0.44
I
OL
=
-
24 mA (Note 2)
I
IN
Maximum Input
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
Leakage Current
I
OZT
Maximum I/O
5.5
0.3
3.0
A
V
I/O
=
V
CC
or GND
Leakage Current
V
IN
=
V
IH
, V
IL
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 3)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
Maximum Quiescent
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
Supply Current
5
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7
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T323
AC Electrical Characteristics
Note 4: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
Note 5: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
V
CC
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 4)
Min
Typ
Max
Min
Max
f
max
Maximum Input Frequency
5.0
120
125
110
MHz
t
PLH
Propagation Delay
5.0
5.0
9.0
12.5
4.0
14.0
ns
CP to Q
0
or Q
7
t
PHL
Propagation Delay
5.0
5.0
9.0
13.5
4.5
15.0
ns
CP to Q
0
or Q
7
t
PLH
Propagation Delay
5.0
5.0
8.5
12.5
4.5
14.5
ns
CP to I/O
n
t
PHL
Propagation Delay
5.0
6.0
10.0
14.5
5.0
16.0
ns
CP to I/O
n
t
PZH
Output Enable Time
5.0
3.5
7.5
11.0
3.0
12.5
ns
t
PZL
Output Enable Time
5.0
3.5
7.5
11.5
3.0
13.0
ns
t
PHZ
Output Disable Time
5.0
4.0
8.5
12.5
3.0
13.5
ns
t
PLZ
Output Disable Time
5.0
3.0
8.0
11.5
2.5
12.5
ns
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
V
CC
C
L
=
50 pF
C
L
=
50 pF
Units
(V)
V
CC
=
+
5.0V
V
CC
=
+
5.0V
(Note 5)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0
2.0
5.0
5.0
ns
S
0
or S
1
to CP
t
H
Hold Time, HIGH or LOW
5.0
0
1.5
1.5
ns
S
0
or S
1
to CP
t
S
Setup Time, HIGH or LOW
5.0
1.0
4.0
4.5
ns
I/O
n
, DS
0
, DS
7
to CP
t
H
Hold Time, HIGH or LOW
5.0
0
1.0
1.0
ns
I/O
n
, DS
0
, DS
7
to CP
t
S
Setup Time, HIGH or LOW
5.0
1.0
2.5
2.5
ns
SR to CP
t
H
Hold Time, HIGH or LOW
5.0
0
1.0
1.0
ns
SR to CP
t
W
CP Pulse Width
5.0
2.0
4.0
4.5
ns
HIGH or LOW
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
OPEN
C
PD
Power Dissipation Capacitance
170
pF
V
CC
=
5.0V
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