Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
JANUARY 2003
REV. 4.0.0
GENERAL DESCRIPTION
The ST16C1550 and ST16C1551 UARTs (here on
denoted as the ST16C155X) are improved versions
of the SSI 73M155X and SSI 73M2550 UART with
higher operating speed and lower access time. The
ST16C155X provides enhanced UART functions with
16 byte FIFOs, a modem control interface,
independent programmable baud rate generators
with clock rates up to 1.5 Mbps. Onboard status
registers provide the user with error indications and
operational status. System interrupt and modem
control features may be tailored by external software
to meet specific user requirements. An internal
loopback capability allows onboard diagnostics. The
baud rate generator can be configured for either
crystal or external clock input with the exception of
the 28 pin ST16C1551 package (where an external
clock must be provided). Each package type, with the
exception of the 28 pin ST16C155X, provides a
buffered reset output that can be controlled through
user software. DMA monitor signals TXRDY/RXRDY
are not available at the ST16C155X I/O pins but
these signals are accessible through ISR register bits
4-5. Except as listed above, all package versions
have the same features. The ST16C155X is not a
MS Windows compatible UART. For a MS Windows
compatible UART, please use to the ST16C550.
FEATURES
Pin and functionally compatible to SSI 73M1550/
2550
16 byte Transmit FIFO
16 byte Receive FIFO with error flags
4 selectable Receive FIFO interrupt trigger levels
Modem Control Signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8) with
even, odd or no parity
Crystal or external clock input (except 28 pin
ST16C1551, external clock only)
1.5 Mbps Transmit/Receive operation (24 MHz)
with programmable clock control
Power Down Mode (50 uA at 3.3 V, 200 uA at 5 V)
Software controllable reset output
2.97 to 5.5 Volt operation
APPLICATIONS
Battery Operated Electronics
Internet Appliances
Handheld Terminal
Personal Digital Assistants
Cellular Phones DataPort
F
IGURE
1. B
LOCK
D
IAGRAM
XTAL1/C LK
XTAL2
Crystal Osc/B uffer
DTR #, RTS#
DSR #, CTS#,
CD #, RI#
Data B us
Interface
16 Byte TX FIFO
Baud R ate G enerator
Transmitter
UA RT
Configuration
Regs
IO R#
16 Byte RX FIFO
Receiver
M odem C ontrol Signals
TX
RX
INT
A2:A0
D7:D0
CS#
IO W #
RES ET
RST
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
REV. 4.0.0
5
PIN DESCRIPTIONS
N
AME
28-P
IN
PDIP
(1550)
28-P
IN
PDIP
(1551)
28-P
IN
PLCC
(1550)
28-P
IN
PLCC
(1551)
48-P
IN
TQFP
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A0
A1
A2
21
20
19
21
20
19
21
20
19
21
20
19
30
28
27
I
Address data lines [2:0]. A2:A0 selects internal UART's
configuration registers.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
43
45
46
47
3
4
5
6
I/O
Data bus lines [7:0] (bidirectional).
IOR#
16
15
16
15
20
I
Input/Output Read (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], places
it on the data bus to allow the host processor to read it on
the leading edge.
IOW#
14
13
14
13
17
I
Input/Output Write (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the
data byte on the data bus to an internal register pointed by
the address lines [A2:A0].
CS#
11
11
11
11
9
I
Chip Select input (active low). A logic 0 on this pin selects
the ST16C155X device.
INT
18
18
18
18
23
O
Interrupt Output (three-state, active high). INT output
defaults to three-state mode and becomes active high when
MCR bit-3 is set to a logic 1. INT output becomes a logic
high level when interrupts are enabled in the interrupt
enable register (IER), and whenever the transmitter,
receiver, line and/or modem status register has an active
condition.
MODEM OR SERIAL I/O INTERFACE
TX
10
10
10
10
8
O
Transmit Data. This output is associated with individual
serial transmit channel data from the 155X. The TX signal
will be a logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local loopback mode, the
TX output pin is disabled and TX data is internally con-
nected to the UART RX input.
RX
9
9
9
9
7
I
Receive Data. This input is associated with individual serial
channel data to the 155X. Normal received data input idles
at logic 1 condition. This input must be connected to its idle
logic state, logic 1, else the receiver may report "receive
break" and/or "error" condition(s).
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