Et r onT ech
EM566168
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
1M x 16 Pseudo SRAM
Preliminary, Rev 0.2
Apr. 2002
Features
Organized as 1M words by 16 bits
Fast Cycle Time : 70ns
Standby Current : 100uA
Deep power-down Current : 10uA (Memory cell data
invalid)
Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15)
Compatible with low power SRAM
Single Power Supply Voltage : 3.0V
0.3V
Package Type : 48-ball FBGA, 6x8mm
Pin Description
Symbol
Function
A0 A19
Address Inputs
DQ0 DQ15
Data Inputs/Outputs
CE1#
Chip Enable
CE2
Deep Power Down
OE# Output
Enable
WE# Write
Control
LB#
Lower Byte Control
UB#
Upper Byte Control
V
CC
Power
Supply
V
SS
Ground
Pin Assignment 48-Ball BGA, Top View
Overview
The EM566168 is a 16M-bit Pseudo SRAM organized as 1M words by 16 bits. It is designed with advanced
CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This
device operates from a single power supply. Advanced circuit technology provides both high speed and low
power. It is automatically placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2
is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output enable
(OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access.
This device is well suited to various microprocessor system applications where high speed, low power and
battery backup are required. And, with a guaranteed wide operating range, the EM566168 can be used in
environments exhibiting extreme temperature conditions.
Pin Location
Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location
A0 A3 A8 H2 A16 E4 DQ3 D5 DQ11 D2 WE# G5
A1 A4 A9 H3 A17 D3 DQ4 E5 DQ12 E2 LB# A1
A2 A5 A10 H4 A18 H1 DQ5 F5 DQ13 F2 UB# B2
A3 B3 A11 H5 A19 G2 DQ6 F6 DQ14 F1 VCC D6
A4 B4 A12 G3 NC H6 DQ7 G6 DQ15 G1 VCC E1
A5 C3 A13 G4 DQ0 B6 DQ8 B1 CE1# B5 GND D1
A6 C4 A14 F3 DQ1 C5 DQ9 C1 CE2 A6 GND E6
A7 D4 A15 F4 DQ2 C6
DQ10
C2 OE# A2 NC E3
6
5
4
3
2
1
LB#
OE#
DQ8
UB#
A0
A1
A3
A4
A2
CE2
CE1#
DQ0
DQ9
DQ10
VSS
DQ11
A5
A6
A17
A7
DQ1
DQ2
DQ3
VCC
VCC
DQ12
DQ14
DQ13
NC
A16
A14
A15
DQ4
VSS
DQ5
DQ6
DQ15
A19
A18
A8
A12
A13
A9
A10
WE#
DQ7
A11
NC
G
H
F
E
D
C
B
A
Et r onT ech
EM566168
Preliminary
2 Rev
0.2
Feb. 2002
Block Diagram
Address
Buffer
Row
Address
Decoder
Memory Cell Array
1M x 16
Input
Data
Control
Sense AMP
Column Decoder
Standby/Deep Power
Down Mode Control
Refresh Control
Refresh
Counter
Output
Data
Control
Address Buffer
Control
Logic
VCC
VSS
A0 A19
DQ0 DQ7
DQ8 DQ15
CS1#
CS2
LB#
OE#
WE#
UB#
Et r onT ech
EM566168
Preliminary
3 Rev
0.2
Feb. 2002
Operating Mode
CS1# CS2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15
Mode
Power
H H X X X X High-Z High-Z Deselect
Standby
X L X X X X High-Z High-Z Deselect
Deep
Power
Down
L H X X H H High-Z High-Z Deselect
Standby
L H H H L X High-Z High-Z Output
Disabled
Active
L H H H X L High-Z High-Z Output
Disabled
Active
L H L H L H D-out High-Z Lower
Byte
Read
Active
L H L H H L High-Z D-out Upper
Byte
Read
Active
L H L H L L D-out
D-out Word
Read
Active
L H X L L H D-in
High-Z Lower
Byte
Write
Active
L H X L H L High-Z
D-in Upper
Byte
Write
Active
L H X L L L D-in
D-in Word
Write
Active
Note: X=don't care. H=logic high. L=logic low.
Absolute Maximum Ratings
1)
Supply voltage, V
CC
-0.2 to +3.6V
Input voltages, V
IN
-0.2 to VCC + 0.3V
Input and output voltages, V
IN
, V
OUT
-2.0 to +3.6V*
Output short circuit current I
SH
100
mA
Operating temperature, T
A
-25 to +85
C
Storage temperature, T
STRG
-65 to +125
C
Soldering Temperature (10s), T
SOLDER
240
C
Power dissipation, P
D
1
W
Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute
maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device
reliability.
Recommended DC Operating Conditions
Symbol Parameter
Min.
Typ.
Max.
Unit
V
CC
Power Supply Voltage
2.7
3.0
3.3
V
V
SS
Ground
0
-
0 V
V
IH
Input High Voltage
2.2
-
V
CC
+0.2
1)
V
V
IL
Input Low Voltage
-0.2
2)
-
+0.6 V
Notes:
1. Overshoot: VCC + 2.0V in case of pulse width
20ns
2. Undershoot: -2.0V in case of pulse width
20ns
3. Overshoot and undershoot are sampled, not 100% tested.
Et r onT ech
EM566168
Preliminary
4 Rev
0.2
Feb. 2002
DC Characteristics
Symbol
Parameter Test
Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
VIN = VSS to VDD
-1 1
A
ILO
Output Leakage Current
VIO = VSS to VDD
CE1# = VIH, CE2 = VIL or
OE# = VIH or WE# = VIL
-1 1
A
ICC1
Operating Current @ Min
Cycle Time
Cycle time = Min., 100% duty
IIO = 0mA, CE1# = VIL,
CE2 = VIH, VIN = VIH or VIL
-
25 mA
ICC2
Operating Current @ Max
Cycle Time (1
s)
Cycle time = 1
s, 100% duty
IIO = 0mA, CE1#
0.2V,
CE2
VDD
-0.2V, VIN
0.2V
or VIN
VDD
-0.2V
-
3 mA
ISB1
Standby Current (CMOS)
CE1# = VDD 0.2V and
CE2 = VDD 0.2V,
Other inputs = VSS ~ VCC
-
100
A
ISBD
Deep Power Down
CE2
0.2V, Other inputs =
VSS ~ VCC
10
A
VOL
Output Low Voltage
IOL = 2.1mA
-
0.4
V
VOH
Output High Voltage
IOH = -1.0mA
2.4
-
V
Capacitance (Ta = 25
C; f = 1 MHz)
Parameter Symbol
Min
Typ
Max
Unit
Test
Conditions
Input capacitance
CIN
-
-
8 pF
VIN = GND
Output capacitance
COUT
-
-
10 pF VOUT = GND
Notes: These parameters are sampled and not 100% tested.
Et r onT ech
EM566168
Preliminary
5 Rev
0.2
Feb. 2002
AC Characteristics and Operating Conditions (Ta = -25
C to 85
C, VCC = 2.7V to 3.3V)
-85 -70
Symbol
Parameter
Min Max Min Max
Unit
Read Cycle
tRC
Read cycle time
85
-
70
-
ns
tAA
Address access time
-
85
-
70 ns
tCO1
Chip Enable (CE1#) Access Time
-
85
-
70 ns
tCO2
Chip Enable (CE2) Access Time
-
85
-
70 ns
tOE
Output enable access time
-
40
-
35 ns
tBA
Data Byte Control Access Time
-
85
-
70 ns
tLZ
Chip Enable Low to Output in Low-Z
10
-
10
-
ns
tOLZ
Output enable Low to Output in Low-Z
5
-
5
-
ns
tBLZ
Data Byte Control Low to Output in Low-Z
10
-
10
-
ns
tHZ
Chip Enable High to Output in High-Z
-
35
-
25 ns
tOHZ
Output Enable High to Output in High-Z
-
35
-
25 ns
tBHZ
Data Byte Control High to Output in High-Z
-
35
-
25 ns
tOH
Output Data Hold Time
10
-
10
-
ns
Write Cycle
tWC
Write Cycle Time
85
-
70
-
ns
tWP
Write Pulse Width
60
-
50
-
ns
tAW
Address Valid to End of Write
70
-
60
-
ns
tCW
Chip Enable to End of Write
70
-
60
-
ns
tBW
Data Byte Control to End of Write
70
-
60
-
ns
tAS
Address Setup Ttime
0
-
0
-
ns
tWR
Write Recovery Time
0
-
0
-
ns
tWHZ
WE# Low to Output in High-Z
-
30
-
20 ns
tOW
WE# High to Output in Low-Z
5
-
5
-
ns
tDW
Data to Write Overlap
30
-
30
-
ns
tDH
Data Hold Time
0
-
0
-
ns
AC Test Condition
Output load : 50pF + one TTL gate
Input pulse level : 0.4V, 2.4
Timing measurements : 0.5 x VCC
tR, tF : 5ns
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