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BLOCK DIAGRAM

496 Byte

EEPROM Array

Logic

SCL

SDA

RST

Interface

Data Transfer

Array Access

Enable

ISO Reset

Response Register

Password Array

and Password

Verification Logic

Retry Counter

Erase Logic

X76F400

512 x 8 bit

Secure SerialFlash

FEATURES

·64-bit password security
·One array (496 bytes) two passwords (16 bytes)

--Read password
--Write password

·Programmable passwords
·Retry counter register

--Allows 8 tries before clearing of the array

·32-bit response to reset (RST input)
·8 byte sector write mode

·1MHz clock rate ·2-wire
serial interface ·Low
power CMOS

--2.5 to 5.5V operation
--Standby current less than 1µA
--Active current less than 3 mA

·High reliability endurance:

--100,000 write cycles

·Data retention: 100 years
·Available in:

--8-lead, SOIC,TSSOP

DESCRIPTION

The X76F400 is a password access security supervisor,
containing one 3968-bit Secure Serial Flash array.

Access to the memory array can be controlled by two 64-bit
passwords. These passwords protect read and

write operations of the memory array.

The X76F400 features a serial interface and software
protocol allowing operation on a popular 2-wire bus.

The bus signals are a clock input (SCL) and a bi-directional
data input and output (SDA).

The X76F400 also features a synchronous response to
reset, providing an automatic output of a hard-wired

32-bit data stream, thereby meeting the industry standard
for memory cards.

The X76F400 utilizes Xicor's proprietary Direct Write

cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.

This X76F400 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.

mic

IC MICROSYSTEMS

X76F400

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PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the
device.

Serial Data (SDA)

SDA is an open drain serial data input/output pin. During a
read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.

Reset (RST)

RST is a device reset pin. When RST is pulsed high, the
X76F400 will output 32 bits of fixed data, which

conforms to the standard for "synchronous response-
to-reset." The part must not be in a write cycle for the

response-to-reset to occur. See Figure 7. If power is
interrupted during the response-to-reset, the response-

to-reset will be aborted and the part will return to the
standby state. The response to reset is "mask
programmable" only!

DEVICE OPERATION

The X76F400 memory array consists of 62 8-byte sectors.
Read or write access to the array always begins at

the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8 bytes.

There are two primary modes of operation for the
X76F400; Protected READ and protected WRITE. Pro-

tected operations must be performed with one of two 8- byte
passwords.

The basic method of communication for the device is
generating a start condition, then transmitting a com-

mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to `0.'

The user must perform ACK polling to determine the
validity of the password, prior to starting a data transfer

(see Acknowledge Polling). Only after the correct password
is accepted, and an ACK polling has been

performed, can the data transfer occur. See Figure 1.

To ensure the correct communication, RST must
remain LOW under all conditions except when running

a "response-to-reset sequence".

Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving

device.

If the X76F400 is in a nonvolatile write cycle a "no ACK"
(SDA = High) response will be issued in

response to loading of the command byte. If a stop is issued
prior to the nonvolatile write cycle, the write

operation will be terminated; the part will then reset and
enter into a standby mode.

(The basic sequence is illustrated in Figure 1.)

PIN NAMES

PIN CONFIGURATION

After each transaction is completed, the X76F400 will
reset and enter into a standby mode. This will also be

the response if an unsuccessful attempt is made to
access a protected array.

Symbol

Description

SDA

Serial Data Input/Output

SCL

Serial Clock Input

RST

Reset Input

Supply Voltage

Ground

No Connect

SDA

RST

SCL

SOIC

RST

SDA

SCL

TSSOP

X76F400

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Figure 1. X76F400 Device Operation

Retry Counter

The X76F400 contains a retry counter. The retry
counter allows 8 accesses with an invalid password

before any action is taken. The counter will increment with
any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of the
passwords are cleared to "0." If a correct password

is received prior to retry counter overflow, the retry
counter is reset and access is granted.

Device Protocol

The X76F400 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer

is a master and the device being controlled is the slave.
The master will always initiate data transfers and

provide the clock for both transmit and receive operations.
Therefore, the X76F400 will be considered a
slave in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are

reserved for indicating start and stop conditions. Refer to
Figures 2 and 3.

Start Condition

All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is

HIGH. The X76F400 continuously monitors the SDA and
SCL lines for the start condition, and will not

respond to any command until this condition is met.

A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset

the device and leave it ready to begin a new read or write
command. Because of the push/pull output, a

start cannot be generated while the part is outputting data.
Starts are inhibited while a write is in progress.

Stop Condition

All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition

of SDA when SCL is HIGH. The stop condition is also used
to reset the device during a command or data

input sequence, leaving the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.

Acknowledge

Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting 8 bits.
During the ninth clock cycle the receiver will pull

the SDA line LOW to acknowledge that it received the 8
bits of data.

The X76F400 will respond with an acknowledge after
recognition of a start condition and its slave address. If

both the device and a write condition have been
selected, the X76F400 will respond with an acknowl-

edge after the receipt of each subsequent 8-bit word.

Load Command/Address Byte

Load 8-Byte

Password

Verify Password

Acceptance by

Use of ACK Polling

Read/Write

Data Bytes

Figure 2. Data Validity

SCL

SDA

Data Stable

Data

Change

X76F400

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Figure 3. Definition of Start and Stop Conditions

Table 1. X76F400 Instruction Set

Command After Start

Command Description

Password Used

1 S

Sector Write

Write

1 S

Sector Read

Read

1 1 1 1 1 1 0 0

Change Write Password

Write

1 1 1 1 1 1 1 0

Change Read Password

Write

0 1 0 1 0 1 0 1

Password ACK Command

None

SCL

SDA

START Condition

STOP Condition

Illegal command codes will be disregarded. The part will
respond with a "no-ACK" to the illegal byte and

then return to the standby mode. All write/read operations
require a password.

PROGRAM OPERATIONS

Sector Write

The sector write mode requires issuing the 8-bit write
command followed by the password and then the data

bytes transferred as illustrated in Figure 4. The write
command byte contains the address of the sector to be

written. Data is written starting at the first address of a
sector and 8 bytes must be transferred. After the last
byte to be transferred is acknowledged, a stop condition is
issued which starts the nonvolatile write cycle. If
more or less than 8 bytes are transferred, the data in the
sector remains unchanged.

ACK Polling

Once a stop condition is issued to indicate the end of the
host's write sequence, the X76F400 initiates the

internal nonvolatile write cycle. In order to take advantage of
the typical 5ms write cycle, ACK polling can

begin immediately. This involves issuing the start condition
followed by the new command code of 8 bits

(first byte of the protocol). If the X76F400 is still busy

with the nonvolatile write operation, it will issue a "no-
ACK" in response. If the nonvolatile write operation is
completed, an "ACK" will be returned and the host can then
proceed with the rest of the protocol.

Data ACK Polling Sequence

ACK

Returned?

Issue New

Command Code

Write Sequence

Completed Enter ACK

Polling

Issue START

YES

PROCEED

X76F400

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After the password sequence, there is always a nonvola- tile
write cycle. This is done to discourage random

guesses of the password if the device is being tampered with.
In order to continue the transaction, the X76F400

requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As

with regular acknowledge polling the user can either time
out for 10ms and then issue the ACK polling once,

or continuously loop as described in the flow.

If the password inserted is correct, the nonvolatile cycle
in response to the password ACK polling
sequence is over, and an "ACK" is returned.

If the password inserted is incorrect, a "no ACK" is
returned, even if the nonvolatile cycle is over. There-

fore, the user cannot be certain that the password is
incorrect until the 10ms write cycle time has elapsed.

Password ACK Polling Sequence

READ OPERATIONS

Read operations are initiated in the same manner as
write operations but with a different command code.

Sector Read

With sector read, a sector address is supplied with the read
command. Once the password has been

acknowledged data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A

read operation always begins at the first byte in the
sector, but may stop at any time. Random accesses to

the array are not possible. Continuous reading from the
array will return data from successive sectors. After

reading the last sector in the array, the address is auto-
matically set to the first sector in the array and data can

continue to be read out. After the last bit has been read,
a stop condition is generated without sending a

preceding acknowledge.

ACK

Returned?

Issue Password
ACK Command

Password Load

Completed Enter ACK

Polling

Issue START

YES

PROCEED

X76F400

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Figure 4. Sector Write Sequence (Password Required)

Figure 5. Acknowledge Polling

Figure 6. Sector Read Sequence (Password Required)

Write

Password

Write

Password

SDA

Wait t

ACK

Password

Command

Password ACK

Command

If ACK, then

Password Matches

Command

Host

Commands

Host

Commands

X76F400

Response

X76F400

Response

Wait t

Data

ACK Polling

CLK of

Pwd. Byte

`ACK'

CLK

`ACK'

CLK

`ACK'

START

Condition

Bit

ACK or

No ACK

SCL

SDA

Data n

Read

Password

Read

Password

Data 0

SDA

Wait t

ACK

Password

Command

Password ACK

Command

If ACK, then

Password Matches

Command

Host

Commands

Host

Commands

X76F400

Response

X76F400

Response

-
A

X76F400

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PASSWORDS

Passwords are changed by sending the "change read
password" or "change write password" commands in a
normal sector write operation. A full 8 bytes containing the
new password must be sent, following successful
transmission of the current write password and a valid
password ACK response. The user can use a repeated

ACK polling command to check that a new password has
been written correctly. An ACK indicates that the

new password is valid.

There is no way to read any of the passwords.

RESPONSE-TO-RESET (DEFAULT = 19 40 AA 55)

The ISO Response-to-reset is controlled by the RST and
CLK pins. When RST is pulsed high during a clock

pulse, the device will output 32 bits of data, one bit per
clock, and it resets to the standby state. This conforms

to the ISO standard for "synchronous response to reset."
The part must not be in a write cycle for the

response-to-reset to occur.

After initiating a nonvolatile write cycle, the RST pin must
not be pulsed until the nonvolatile write cycle is

complete. If not, the ISO response will not be activated.
If the RST is pulsed HIGH and the CLK is within

the RST pulse (meet the t

NOL spec.) in the middle of an

ISO transaction, it will output the 32 bit sequence again
(starting at bit 0). Otherwise, this aborts the ISO

operation and the part returns to standby state. If the RST
is pulsed HIGH and the CLK is outside the RST
pulse (in the middle of an ISO transaction), this aborts the
ISO operation and the part returns to standby
state.

If power is interrupted during the response-to-reset, the
response-to-reset will be aborted and the part will

return to the standby state. A response-to-reset is not
available during a nonvolatile write cycle.

Figure 7. Response to RESET (RST)

SCK

RST

Byte

MSB

LSB

MSB

LSB

MSB LSB

MSB

0000

1 0

X76F400

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ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... 65°C to +135°C
Storage temperature ........................ 65°C to +150°C

Voltage on any pin with

respect to V

......................................... 1V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds) ......... 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the
device (at these or any other conditions above those

listed in the operational sections of this specification) is not
implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

+70°C

Industrial

40°C

+85°C

Supply Voltage

Limits

X76F400

4.5V to 5.5V

X76F400 2.5

2.5V to 5.5V

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V

Notes:

(1)Must perform a stop command after a read command prior to measurement (2)V

min. and V

max. are for reference only and are not tested

(3)This parameter is periodically sampled and not 100% test

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Max.

CC1

CC Supply current

(Read)

SCL

= V

x 0.1/V

x 0.9 Levels @ 400 kHz,

SDA = Open
RST = V SS

CC2

(3)

CC Supply current

(Write)

SCL

= V

x 0.1/V

x 0.9 Levels @ 400 kHz,

SDA = Open
RST = V SS

SB1

(1)

CC Supply current

(Standby)

µA

= V

x 0.1, V

= V

x 0.9

SCL

= 400 kHz, f

SDA

= 400 kHz

SB2

(1)

CC Supply current

(Standby)

µA

SDA

= V

SCC

= V

Other = GND or V

0.3V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

(2)

Input LOW voltage

0.5

x 0.1

(2)

Input HIGH voltage

x 0.9 V

+ 0.5

Output LOW voltage

0.4

= 3mA

Symbol

Test

Max.

Unit

Conditions

OUT

(3)

Output capacitance (SDA)

I/O

= 0V

(3)

Input capacitance (RST, SCL)

= 0V

X76F400

Characteristics subject to change without notice.

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EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

1.3K

Output

100pF

1.53K

Output

100pF

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

Output load

100pF

AC CHARACTERISTICS (T

= -40°C to +85°C, V

= +2.5V to +5.5V, unless otherwise specified)

Notes: (1)C

= total capacitance of one bus line in pF

(2)t

= 1.1µs Max below V

= 2.5V.

RESET AC SPECIFICATIONS

Power Up Timing

Notes: (1)Delays are measured from the time V

is stable until the specified operation can be initiated. These parameters are periodically sampled

and not 100% tested.

(2)Typical values are for T

= 25°C and V

= 5.0V

Symbol

Parameter

Min.

Max.

Unit

SCL

SCL clock frequency

MHz

AA(2)

SCL LOW to SDA data out valid

0.1

0.9

µs

BUF

Time the Bus must be free before a new transmission can start

1.2

µs

HD:STA

Start condition hold time

0.6

µs

LOW

Clock LOW period

1.2

µs

HIGH

Clock HIGH period

0.6

µs

SU:STA

Start condition setup time (for a repeated start condition)

0.6

µs

HD:DAT

Data in hold time

SU:DAT

Data in setup time

100

SDA and SCL rise time

20+0.1XC

(1)

300

SDA and SCL fall time

20+0.1XC

(1)

300

SU:STO

Stop condition setup time

0.6

µs

Data out hold time

µs

NOL

RST to SCL non-overlap

500

RDV

RST LOW to SDA valid during response to reset

450

CDV

CLK LOW to SDA valid during response to reset

450

RST

RST high time

1.5

µs

SU:RST

RST setup time

500

Symbol

Parameter

Min.

Typ.

(2)

Max.

Unit

PUR

(1)

Time from power up to read

PUW

(1)

Time from power up to write

X76F400

Characteristics subject to change without notice.

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Nonvolatile Write Cycle Timing

Note:

(1)t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Bus Timing

Write Cycle Timing

RST Timing Diagram--Response to a Synchronous Reset

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

(1)

Write cycle time

SU:STA

HD:STA

HD:DAT

SU:DAT

LOW

SU:STO

BUF

SCL

SDA IN

SDA OUT

HIGH

SCL

SDA

Bit of Last Byte

ACK

STOP

Condition

START

Condition

RST

NOL

HIGH_RST

LOW_RST

CDV

RDV

SU:RST

Data Bit (1)

Data Bit (2)

CLK

Pulse

CLK

Pulse

CLK

Pulse

I/O

CLK

RST

NOL

X76F400

Characteristics subject to change without notice.

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LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory,
implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of
merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others
belong to their respective owners.

U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706;
4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774;
5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.
1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical

component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

REV 1.0 7/5/00

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Ordering Information

Part Mark Convention

Limits

Blank = 5V ±10%
2.5 = 2.5V to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial= 40°C to +85°C

Package
S8 = 8-Lead SOIC
V8 = 8-Lead TSSOP

H = Die in waffle packs (Contact Factory)
W = Die in wafer form (Contact Factory)

Device

X76F400

T G V

8-Lead TSSOP

YWW

8-Lead SOIC

X76F400 XG

Blank = 8-Lead SOIC
G = RoHS compliant lead free

AE = 2.5 to 5.5V, 0 to +70°C
AF = 2.5 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C

Blank = 4.5 to 5.5V, 0 to 70°C
I = 4.5 to 5.5V, -40 to +85°C
AE = 2.5 to 5.5V, 0 to 70°C
AF = 2.5 to 5.5V, -40 to +85°C

7640XX

RoHS Compliant Lead Free package
Blank Standard package. Non lead free

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