High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
1
GENERAL DESCRIPTION
The
WS6264
is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 8,192 words by 8bits and operates from a single 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features and
maximum access time of 70ns in 5.0V operation. Easy memory expansion is provided by using two chip
enable inputs (/CE1, CE2) and active LOW output enable (/OE).
The
WS6264
has an automatic power down feature, reducing the power consumption significantly
when chip is deselected. The
WS6264
is available in JEDEC standard 28-pin SOP(300 mil) and PDIP
(600 mil) packages.
FEATURES
Operation voltage : 4.5 ~ 5.5V
Ultra low power consumption:
Operating current 1mA@1MHz & CMOS standby current 1.0uA (Typ.) in Vcc=5.0V
High speed access time: 70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 2.0V.
Easy expansion with /CE1, CE2 and /OE options.
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed (ns)
Standby Current (Typ.)
I
CCSB1
Package Type
28 SOP
0~70
o
C 70
1.0uA
28 SOP
28 PDIP
WS6264LLP
-40~85
o
C
4.5~5.5V
70 1.0uA
28 PDIP
WS6264LLFPI
WS6264LLFP
WS6264LLPI
Rev. 1.0
2
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
23
17
15
16
20
18
19
22
21
25
24
26
28
27
A11
DQ5
DQ4
DQ3
CE1
DQ7
DQ6
A10
OE
CE2
A9
A8
WE
VCC
A4
DQ1
GND
DQ2
A1
DQ0
A0
A3
A2
A6
A5
A7
NC
A12
28L SOP
28L PDIP
FUNCTIONAL BLOCK DIAGRAM
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
128 x512
Rev. 1.0
3
PIN DESCRIPTIONS
Name
Type
Function
A0 A12
Input
Address inputs for selecting one of the 8,192 x 8 bit words in the RAM
/CE1,CE2
Input
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is not
active, the device is deselected and in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
/WE
Input
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE
Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0~DQ7
I/O
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Vcc
Power Power
Supply
Gnd
Power Ground
NC
No
connection
TRUTH TABLE
MODE
/CE1
CE2
/WE
/OE
DQ0~7
Vcc Current
H X X X
Standby
X L X X
High Z
I
CCSB
, I
CCSB1
Output
Disable
L H H H
High
Z
I
CC
Read
L H H L
D
OUT
I
CC
Write
L H L X
D
IN
I
CC
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
4
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Rating
Unit
V
TERM
Terminal Voltage with Respect to GND
-0.5 to Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-65 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
Vcc
Commercial
0~70
o
C
4.5 ~ 5.5V
Industrial
-40~85
o
C
4.5 ~ 5.5V
CAPACITANCE
(1)
(TA=25,f=1.0MHz)
Symbol
Parameter
Conduction
MAX.
Unit
C
IN
Input Capacitance
VIN=0V
8
pF
C
DQ
Input/Output Capacitance
VDI/O=0V
10
pF
1.This parameter is guaranteed, and not 100% tested.
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
5
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
~70
o
C, Vcc = 5.0V) )
Name
Parameter
Test Condition
MIN
TYP
(1)
MAX
Unit
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=5.0V
-0.5
0.8
V
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=5.0V
2.2 Vcc+0.5
V
I
IL
Input Leakage Current
V
CC
=MAX, V
IN
=0 to V
CC
-1 1 uA
I
OL
Output Leakage Current
V
CC
=MAX, /CE1=V
Ih
, or
CE2= V
IL,
or /OE=V
Ih
,or
/WE= V
IL
V
IO
=0V to V
CC
-1 1 uA
V
OL
Output Low Voltage
V
CC
=MAX, I
OL
= 1mA
0.4
V
V
OH
Output High Voltage
V
CC
=MIN, I
OH
= -1mA
2.4
V
I
CC
Operating Power Supply
Current
/CE1=V
IL
, I
DQ
=0mA,
F=F
MAX
=1/ t
RC
30
mA
I
CCSB
TTL Standby Supply
/CE1=V
IH
, I
DQ
=0mA,
10
mA
I
CCSB1
CMOS Standby Current
/CE1V
CC
-0.2V, CE2= 0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V,
1 10
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are
included.
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
6
DATA RETENTION CHARACTERISTICS
( TA = 0
o
~70
o
C, Vcc = 5.0V) )
Name
Parameter
Test Condition
MIN TYP
(1)
MAX
Unit
V
DR
V
CC
for Data Retention
/CE1 V
CC
-0.2V, V
IN
V
CC
-0.2V or V
IN
0.2V
2.0 V
I
CCDR
Data Retention Current
/CE1V
CC
-0.2V, V
IN
V
CC
-0.2V or V
IN
0.2V
0.5 5 uA
T
CDR
Chip Deselect to Data
Retention Time
0 ns
t
R
Operation
Recovery
Time
Refer to
Retention Waveform
t
RC
(2)
ns
1.
TA = 25
o
C
2.
t
RC= .
Read Cycle Time
LOW Vcc DATA RETENTION WAVEFORM(1)
( /CE1 Controlled )
Data Retention Mode
CE1
V
t
CDR
t
R
IH
V
IH
DR
V > 2.0V
V
CC
CE1
> - 0.2V
CC
V
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
7
LOW Vcc DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
CE2
V
t
CDR
t
R
IL
V
IL
DR
V > 2.0V
V
CC
CE2
< 0.2v
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc/0V
WAVEFORMS
INPUTS
OUTPUTS
Input Rise and Fall Times
5ns
MUST BE STEADY MUST BE STEADY
Input and Output Timing
Reference Level
0.5Vcc
Output Load
See FIGURE 1A
and 1B
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON'T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
8
AC TEST LOADS AND WAVEFORMS
5V
OUTPUT
3857
1500
30p
F
INCLUDING
JIG AND
SCOPE
FIGURE 1A
5V
OUTPUT
3857
1500
5p
F
INCLUDING
JIG AND
SCOPE
FIGURE 1B
AC ELECTRICAL CHARACTERISTICS
(
0~70Vcc=5V
)
< READ CYCLE >
-70
JEDEC
Name
Symbol
Description
MIN
MAX
Unit
t
AVAX
t
RC
Read Cycle Time
70
ns
t
AVQV
t
AA
Address Access Time
70
ns
t
ELQV
t
ACE
Chip Select Access Time
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
40
ns
t
ELQX
t
CLZ
(5)
Chip Select to Output Low Z
10
ns
t
GLQX
t
OLZ
(5)
Output Enable to Output in Low Z
5
ns
t
EHQZ
t
CHZ
(5)
Chip Deselect to Output in High Z
0
35
ns
t
GHQZ
t
OHZ
(5)
Output Disable to Output in High Z
0
30
ns
t
AXOX
t
OH
Address Change to Out Disable
10
ns
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
9
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
[1,2,4]
READ CYCLE 2
[1,3,4]
READ CYCLE 3
[1,4]
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
1 0
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE1 = V
IL
and CE2=V
IH.
3. Address valid prior to or coincident with /CE1 transition low and /or CE2 transition high.
4. /OE = V
IL
.
5.
Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
AC ELECTRICAL CHARACTERISTICS (
0~70Vcc=5V
)
< WRITE CYCLE >
-70
JEDEC
Name
Symbol
Description
MIN
MAX
Unit
t
AVAX
t
WC
Write Cycle Time
70
ns
t
E1LWH
t
CW
Chip Select to End of Write
70
ns
t
AVWL
t
AS
Address Setup Time
0
ns
t
AVWH
t
AW
Address Valid to End of Write
70
ns
t
WLWH
t
WP
Write Pulse Width
50
ns
t
WHAX
t
WR
Write Recovery Time
0
ns
t
WLQZ
t
WHZ
(10)
Write to Output in High Z
35
ns
t
DVWH
t
DW
Data to Write Time Overlap
40
ns
t
WHDX
t
DH
Data Hold for Write End
0
ns
t
GHQZ
t
OHZ
(10)
Output Disable to Output in High Z
0
30
ns
t
WHOX
t
OW
(10)
End of Write to Output Active
5
ns
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
1 1
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
Rev. 1.0
12
NOTES:
1. T
AS
is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE1 and CE2 active and /WE
low. All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. T
WR
is measured from the earlier of /CE1 or /WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the /CE1 low transition or CE2 high transition occurs simultaneously with the /WE low
transitions or after the /WE transition, output remain in a high impedance state.
6. /OE is continuously low (/OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If /CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of /CE1 going low or CE2 going high to the end of write.
ORDER INFORMATION
WS6264L
Package:
FP: 28L SOP-330mil
P: 28L PDIP-600mil
Speed:
Temperature:
I: -40~85C
Blank: 0~70C
L X XX
70: 70ns
X X
Package Material:
R: Lead and Halogen Free
-: Normal
Normal-
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
LL: Low Low power
Rev. 1.0
1 3
PACKAGE DIMENSIONS
28 pin SOP (330 mil) :
UNIT
SYMBOL
mm
Min.
Nom.
Max.
A
2.540
inch
Min.
Nom.
Max.
2.692
2.844
0.100
0.106
0.112
0.102
0.226
0.350
0.004
0.009
0.014
2.362
2.489
2.616
0.093
0.098
0.103
0.35
_
0.50
0.014
_
0.020
0.35
_
0.45
0.014
_
0.018
0.20
_
0.32
0.008
_
0.012
0.20
_
0.28
0.008
_
0.011
17.983
18.110
18.237
0.708
0.713
0.718
8.280
8.407
8.534
0.326
0.331
0.336
11.506
11.811
12.116
0.453
0.465
0.477
1.118
1.270
1.422
0.044
0.050
0.056
0.700
0.964
1.228
0.0276
0.0380
0.0484
1.520
1.720
1.920
0.0598
0.0677
0.0756
_
_
0.1
_
_
0.004
0
_
10
0
_
10
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
y
28 pin PDIP (600mil):
0.590
A1
UNIT
_
Max.
Nom.
Min.
Max.
Nom.
Min.
inch
mm
_
0.010
_
_
0.254
SYMBOL
D
c
B1
B
A2
0.070
0.050
0.060
1.778
1.524
1.270
0.023
0.155
0.013
0.018
0.584
0.457
0.330
3.937
0.145
0.150
3.810
3.683
1.465
0.014
0.356
0.006
0.010
0.152
0.254
37.211
1.455
1.460
37.084
36.957
0.090
0.070
0.080
2.286
1.778
2.032
L
eB
e
E1
E
0.548
0.610
0.540
0.544
13.920
13.818
13.716
15.494
0.600
14.986
15.240
0.140
0.660
16.764
0.620
0.640
15.748
16.256
3.556
0.120
0.130
3.048
3.302
Q1
S
9
0.075
0.065
0.070
1.905
1.778
1.651
9
6
3
6
3
2.540
(TYP)
0.100
(TYP)
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
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