Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

Advanced Information

Preliminary Datasheet

OV7640 Color CMOS VGA (640 x 480) C

AMERA

HIP

OV7141 B&W CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

General Description

The OV7640 (color) and OV7141 (black and white)
C

AMERA

HIPS

are low voltage CMOS image sensors

that provide the full functionality of a single-chip VGA
(640 x 480) camera and image processor in a small
footprint package. The OV7640/OV7141 provides
full-frame, sub-sampled or windowed 8-bit images in a
wide range of formats, controlled through OmniVision's
Serial Camera Control Bus (SCCB) interface.

This product family has an image array capable of
operating at up to 30 frames per second (fps) with
complete user control over image quality, formatting and
output data transfer. All required image processing
functions, including exposure control, gamma, white
balance, color saturation, hue control and more, are also
programmable through the SCCB interface. In addition,
OmniVision C

AMERA

HIP

s use proprietary sensor

technology to improve image quality by reducing or
eliminating common lighting/electrical sources of image
contamination such as fixed pattern noise, smearing,
blooming, etc. to produce a clean, fully stable color image.

Features

High sensitivity for low-light operation

2.5V operating voltage for embedded portable
applications

Standard Serial Camera Control Bus (SCCB)
interface

VGA, QVGA (sub-sampled) and Windowed outputs
with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and
YCbCr (4:2:2) formats

Automatic image control functions including:
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB),
Automatic Brightness Control (ABC), Automatic
Band Filter (ABF) for 60Hz noise and Automatic
Black-Level Calibration (ABLC)

Image quality controls including color saturation,
hue, gamma, sharpness (edge enhancement),
anti-blooming and zero smearing

Ordering Information

Product

Package

OV7640 (Color)

PLCC-28

OV7141 (B&W)

PLCC-28

Applications

Cellular and Picture Phones

Toys

PC Multimedia

Key Specifications

Figure 1 OV7640/OV7141 Pin Diagram

Array Size

640 x 480 (VGA)

Power Supply

Core

2.5VDC + 10%

Analog

2.5VDC + 4%

I/O

2.25V to 3.3V

Power

Requirements

Active

40 mW (30 fps, including
I/O power)

Standby

30 W

Temperature

Range

Operation

-10°C to 70°C

Stable Image

0°C to 50°C

Output Formats (8-bit)

· YUV/YCbCr 4:2:2
· RGB 4:2:2
· Raw RGB Data

Lens Size

1/4"

Maximum Image

Transfer Rate

VGA

30 fps

QVGA

60 fps

Sensitivity

B&W

3.0 V/Lux-sec

Color

1.12 V/Lux-sec

S/N Ratio

46 dB

Dynamic Range

62 dB

Scan Mode

Progressive/Interlaced

Maximum Exposure Interval

523 x t

ROW

Gamma Correction

0.45

Pixel Size

5.6 m x 5.6 m

Dark Current

30 mV/s

Well Capacity

60 Ke

Fixed Pattern Noise

< 0.03% of V

PEAK-TO-PEAK

Image Area

3.6 mm x 2.7 mm

Package Dimensions

11.43 mm x 11.43 mm

I
O

PWDN

VREF

VDD_C

VSYNC

HREF

PCLK

OV7640/OV7141

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

Functional Description

Figure 2

shows the functional block diagram of the OV7640/OV7141 image sensor. The OV7640/OV7141 includes:

Image Sensor Array

(640 x 480 resolution)

Timing Generator

Analog Processing Block

A/D Converters

Output Formatter

Digital Video Port

SCCB Interface

Figure 2 OV7640/OV7141 Functional Block Diagram

Output

Formatter

Column Sense Amps

Timing Generator

MUX

VSYNC

PCLK

HREF

l
e

CLK

SIO_D

SIO_C

RESET

PWDN

Analog Processing

Windowing

SCCB

Interface

Control

Registers

(To all circuits)

VREF

1.0 f

Y[7:0]

Digital Video

Port

A/D

Gain

Gamma

Saturation

Hue

Brightness

Data

Formatting

Image Array

(640 x 480)

Functional Description

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

mni

ision

Image Sensor Array

The OV7640/OV7141 C

AMERA

HIPS

has an active image

array size of 640 columns x 480 rows (307,200 pixels).
However, the full array contains 652 columns and 486
rows, with the extra 6 rows used for black-level calibration
("Optical Black") and color interpolation information.

Figure 3

shows a cross-section of the image sensor array.

Figure 3 Image Sensor Array

Timing Generator

In general, the timing generator controls these functions:

Array control and frame generation (VGA and QVGA
outputs)

Internal timing signal generation and distribution

Frame rate timing

Automatic Exposure Control (AEC)

External timing outputs (VSYNC, HREF and PCLK)

Analog Processing Block

This block performs all analog image functions including:

Automatic Gain Control (AGC)

Automatic White Balance (AWB)

Image quality controls including:

Color saturation

Hue

Gamma

Sharpness (edge enhancement)

Anti-blooming

Zero smearing

Color Filter

Microlens

Photo Diode

A/D Converters

After the Analog Processing Block, the color channel data
signal is fed to two 8-bit Analog-to-Digital (A/D) converters
via the multiplexers, one for the Y/G channel and one
shared by the CrCb/BR channels. These A/D converters
operate at speeds up to 12MHz, and are fully
synchronous to the pixel rate (actual conversion rate is
related to the frame rate).

In addition to the A/D conversion, this block also has the
following functions:

Digital Black-Level Calibration (BLC)

Optional U/V channel delay

Additional A/D range controls

In general, the combination of the A/D Range Multiplier
and A/D Range Control sets the A/D range and maximum
value to allow the user to adjust the final image brightness
as a function of the individual application.

Output Formatter

This block controls all output and data formatting required
prior to sending the image out.

Digital Video Port

These two bits increase I

/ I

drive current and can be

adjusted as a function of the customer's loading:

SCCB Interface

The Serial Camera Control Bus (SCCB) interface controls
the C

AMERA

HIP

operation. Refer to

OmniVision

Technologies Serial Camera Control Bus (SCCB)
Specification

for detailed usage of the serial control port.

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

Pin Description

Table 1

Pin Description

Pin Number

Name

Pin Type

Function/Description

VSS_A

Ground

Analog ground

VDD_A

Analog VDD

No connection

PWDN

Input

Sets device to power down standby mode

No connection

VREF

REF

Internal voltage reference (2.3V). Connect to ground through 1F capacitor

VDD_C

Core VDD

VSYNC

Output

Vertical sync output

HREF

Output

HREF output

PCLK

Output

Pixel clock output

VDD_IO

I/O VDD

CLK

Input

External clock

No connection

RESET

Input

Clears all registers and resets them to their default values.

No connection

VSS_D

Ground

Digital ground

Output

Digital video output bit[7]

Output

Digital video output bit[6]

Output

Digital video output bit[5]

Output

Digital video output bit[4]

Output

Digital video output bit[3]

Output

Digital video output bit[2]

Output

Digital video output bit[1]

Output

Digital video output bit[0]

SIO_C

Input

SCCB serial interface clock

SIO_D

I/O

SCCB serial interface data I/O

No connection

Electrical Characteristics

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

mni

ision

Electrical Characteristics

NOTE:

Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 2

Absolute Maximum Ratings

Ambient Storage Temperature

-40ºC to +125ºC

Supply Voltages (with respect to Ground)

DD-A

DD-C

DD-IO

All Input/Output Voltages (with respect to Ground)

-0.3V to VDD_IO+1V

Lead Temperature, Surface-mount process

+230ºC

ESD Rating, Human Body model

2000V

Table 3

DC Characteristics (0°C < T

< 70°C)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

DD-A

DC supply voltage Analog

2.40

2.5

2.60

DD-C

DC supply voltage Core

2.25

2.5

2.75

DD-IO

DC supply voltage I/O

2.25

3.3

DDA

Active (Operating) Current

See Note

a. V

DD-A

= V

DD-C

= 2.5V, V

DD-IO

= 3.0V

DDA

DD-IO

+ I

DD-C

+ I

DD-A

}, f

CLK

= 24MHz at 30 fps, no I/O loading

DDS-SCCB

Standby Current

See Note

b. V

DD-A

= V

DD-C

= 2.5V, V

DD-IO

= 3.0V

DDS:SCCB

refers to a SCCB-initiated Standby, while I

DDS:PWDN

refers to a PWDN pin-initiated Standby

DDS-PWDN

Standby Current

Input voltage HIGH

CMOS

0.7 x V

DD-IO

Input voltage LOW

0.3 x V

DD-IO

Output voltage HIGH

CMOS

/ I

)

0.9 x V

DD-IO

Output voltage LOW

0.1 x V

DD-IO

Output current HIGH

See Note

Standard Output Loading = 25pF, 1.2K to 3V

Output current LOW

Input/Output Leakage

GND to V

DD-IO

± 1

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

Table 4

Functional and AC Characteristics (0°C < T

< 70°C)

Symbol

Parameter

Min

Typ

Max

Unit

Functional Characteristics

A/D

Differential Non-Linearity

+ 1/2

LSB

A/D

Integral Non-Linearity

+ 1

LSB

AGC

Range

Red/Blue Adjustment Range

Inputs (PWDN, CLK, RESET)

CLK

Input Clock Frequency

MHz

CLK

Input Clock Period

100

CLK:DC

Clock Duty Cycle

S:RESET

Setting time after software/hardware reset

S:REG

Settling time for register change (10 frames required)

300

SCCB (SIO_C and SIO_D - see

Figure 4

)

SIO_C

Clock Frequency

400

KHz

LOW

Clock Low Period

1.3

HIGH

Clock High Period

600

SIO_C low to Data Out valid

100

900

BUF

Bus free time before new START

1.3

HD:STA

START condition Hold time

600

SU:STA

START condition Setup time

600

HD:DAT

Data-in Hold time

SU:DAT

Data-in Setup time

100

SU:STO

STOP condition Setup time

600

SCCB Rise/Fall times

300

Data-out Hold time

Outputs (VSYNC, HREF, PCLK, and Y[7:0] - see

Figure 5

Figure 6

, and

Figure 7

)

PDV

PCLK[ ] to Data-out Valid

Y[7:0] Setup time

Y[7:0] Hold time

PHH

PCLK[ ] to HREF[ ]

PHL

PCLK[ ] to HREF[ ]

AC
Conditions:

: V

DD-A

= V

DD-C

= 2.5V, V

DD-IO

= 3.3V

Rise/Fall Times: I/O: 5ns, Maximum

SCCB: 300ns, Maximum

Input Capacitance: 10pf

Output Loading: 25pF, 1.2K to 3V

CLK

: 24MHz

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

Figure 6 VGA Frame Timing Diagram

Figure 7 QVGA Frame Timing Diagram

Note: As the RGB, YUV and YCbCr formats use the Bayer pattern for interpolation, the first row transferred out on the Y[7:0]

bus will be invalid, as there is no row above Row #1 to provide the 'pair data' required. Because of this, the OV7640
does not enable the HREF signal during the first row read (shown above in the 'invalid data' zone).

VSYNC

Y[7:0]

HREF

525 t

ROW

3 t

ROW

11 t

ROW

764 t

PCLK

640 t

PCLK

(Invalid Data)

Row 1

Row 2

Last Row

Row 0

124 t

PCLK

31 t

ROW

(Invalid Data)

VSYNC

Y[7:0]

HREF

262.5 t

ROW

3 t

ROW

9 t

ROW

382 t

PCLK

320 t

PCLK

(Invalid Data)

Row 1

Row 2

Last Row

Row 0

62 t

PCLK

10.5 t

ROW

(Invalid Data)

Timing Specifications

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

mni

ision

Figure 8 RGB 565 Output Timing Diagram

Figure 9 RGB 555 Output Timing Diagram

PCLK

Y[7:0]

Last Byte First Byte

Last Byte

PCLK

PDV

HREF

(Row Data)

PHL

First Byte

Second Byte

Y[5]

Y[4]

Y[3]

Y[2]

Y[7]

Y[6]

Y[1]

Y[0]

Y[5]

Y[4]

Y[3]

Y[2]

Y[7]

Y[6]

Y[1]

Y[0]

PCLK

Y[7:0]

Last Byte First Byte

Last Byte

PCLK

PDV

HREF

(Row Data)

PHL

First Byte

Second Byte

Y[5]

Y[4]

Y[3]

Y[2]

Y[7]

Y[6]

Y[1]

Y[0]

Y[5]

Y[4]

Y[3]

Y[2]

Y[7]

Y[6]

Y[1]

Y[0]

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

Register Set

Table 5

provides a list and description of the Device Control registers contained in the OV7640/OV7141. For all register

Enable/Disable bits, ENABLE=1 and DISABLE=0. The device slave addresses for the OV7640/OV7141 are 42 for write and
43 for read.

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

GAIN

AGC Gain control gain setting

· Range: [00] to [FF]

BLUE

AWB Blue channel gain setting

· Range: [00] to [FF]

Note: This function is not available on the B&W OV7141.

RED

AWB Red channel gain setting

· Range: [00] to [FF]

Note: This function is not available on the B&W OV7141.

SAT

Image Format Color saturation value

Bit[7:4]:

Saturation value
·

Range: [0] to [F]

Bit[3:0]:

Reserved

Note: This function is not available on the B&W OV7141.

HUE

Image Format Color hue control

Bit[7:6]:

Reserved

Bit[5]:

Hue Enable

Bit[4:0]:

Hue setting

Note: This function is not available on the B&W OV7141.

CWF

AWB Red/Blue Pre-Amplifier gain setting

Bit[7:4]:

Red channel pre-amplifier gain setting
·

Range: [0] to [F]

Bit[3:0]:

Blue channel pre-amplifier gain setting
·

Range: [0] to [F]

Note: This function is not available on the B&W OV7141.

BRT

ABC Brightness setting

· Range: [00] to [FF]

07-09

RSVD

Reserved

PID

Product ID number (Read only)

VER

Product version number (Read only)

0C-0F

RSVD

Reserved

AECH

Exposure Value

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

mni

ision

CLKRC

Data Format and Internal Clock

Bit[7:6]:

Data Format HSYNC/VSYNC Polarity
00:

HSYNC = NEG

VSYNC = POS

01:

HSYNC = NEG

VSYNC = NEG

10:

HSYNC = POS

VSYNC = POS

11:

HSYNC = POS

VSYNC = POS

Bit[5:0]:

Internal Clock Pre-Scalar
·

Range: [0 0000] to [F FFFF]

COMA

Common Control A

Bit[7]:

SCCB Register Reset
0:

No change

Reset all registers to default values

Bit[6]:

Output Format Mirror Image Enable

Bit[5]:

Reserved

Bit[4]:

Data Format YUV formatting
0:

Y U Y V Y U Y V

U Y V Y U Y V Y (default)

Bit[3]:

Output Format Output Channel Select A
0:

YUV/YCbCr

RGB/Raw RGB

Bit[2]:

AWB Enable

Bit[1:0]:

Reserved

Note: This function is not available on the B&W OV7141.

COMB

Common Control B

Bit[7:5]:

Reserved

Bit[4]:

Data Format ITU-656 Format Enable

Bit[3]:

Reserved

Bit[2]:

SCCB Tri-State Enable Y[7:0]

Bit[1]:

AGC Enable

Bit[0]:

AEC Enable

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

POS

NEG

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

COMC

Common Control C

Bit[7:6]:

Reserved

Bit[5]:

Output Format Resolution
0:

VGA (640x480)

QVGA (320x240)

Bit[4]:

Reserved

Bit[3]:

Data Format HREF Polarity
0:

HREF Positive

HREF Negative

Bit[2:0]:

Reserved

COMD

Common Control D

Bit[7]:

Data Format Output Flag Bit Disable
0:

Frame = 254 data bits (00/FF = Reserved flag bits)

Frame = 256 data bits

Bit[6]:

Data Format Y[7:0]-PCLK Reference Edge
0:

Y[7:0] data out on PCLK falling edge

Y[7:0] data out on PCLK rising edge

Bit[5:1]:

Reserved

Bit[0]:

Data Format UV Sequence Exchange
0:

V Y U Y V Y U Y

U Y V Y U Y V Y

Note: Bit[0] is not programmable on the B&W OV7141.

RSVD

Reserved

HSTART

Output Format Horizontal Frame (HREF Column) Start

HSTOP

Output Format Horizontal Frame (HREF Column) Stop

VSTRT

Output Format Vertical Frame (Row) Start

VSTOP

Output Format Vertical Frame (Row) Stop

PSHFT

Data Format Pixel Delay Select
(Delays timing of the Y[7:0] data relative to HREF in pixel units)

· Range: [00] (No delay) to [FF] (256 pixel delay)

MIDH

Manufacturer ID Byte High

(Read only = 0x7F)

MIDL

Manufacturer ID Byte Low

(Read only = 0xA2)

RSVD

Reserved

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

POS

NEG

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

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ision

FACT

Output Format Format Control

Bit[7:5]:

Reserved

Bit[4]:

Output Format RGB:565 Enable

Note: Bit[4] is not programmable on the B&W OV7141.

Bit[3]:

Reserved

Bit[2]:

Output Format RGB:555 Enable

Note: Bit[2] is not programmable on the B&W OV7141.

Bit[1:0]:

Reserved

COME

Common Control E

Bit[7]:

Reserved

Bit[6]:

AEC Digital Averaging Enable

Bit[5]:

Reserved

Bit[4]:

Image Quality Edge Enhancement Enable

Bit[3:1]:

Reserved

Bit[0]:

Y[7:0] 2X I

/ I

Enable

21-23

RSVD

Reserved

AEW

AGC/AEC Stable Operating Region Upper Limit

AEB

AGC/AEC Stable Operating Region Lower Limit

COMF

Common Control F

Bit[7:3]:

Reserved

Bit[2]:

Data Format Output Data MSB/LSB Swap Enable
(LSB

MSB (Y[7]) and MSB

LSB (Y[0])

Bit[1:0]:

Reserved

COMG

Common Control G

Bit[7:5]:

Reserved

Bit[4]:

Color Matrix RGB Crosstalk Compensation Enable
(Used to increase each color filter's efficiency)

Note: Bit[4] is not programmable on the B&W OV7141.

Bit[3:2]:

Reserved

Bit[1]:

Data Format Output Full Range Enable
0:

Output Range = [10] to [F0] (224 bits)

Output Range = [01] to [FE] (254/256 bits)

Bit[0]:

Reserved

COMH

Common Control H

Bit[7]:

Output Format RGB Output Select
0:

RGB

Raw RGB

Bit[6]:

Device Select
0:

OV7640

OV7141

Bit[5]:

Output Format Scan Select
0:

Interlaced

Progressive

Bit[4:0]:

Reserved

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

COMI

Common Control I

Bit[7:2]:

Reserved

Bit[1:0]:

Device Version (Read-only)

FRARH

Output Format Frame Rate Adjust High

Bit[7]:

Data Format Frame Rate Adjust Enable

Bit[6:5]:

Data Format Frame Rate Adjust Setting MSB
FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]

Bit[4]:

A/D UV Channel `2 Pixel Delay' Enable

Note: Bit[4] is not programmable on the B&W OV7141.

Bit[3:0]:

Reserved

FRARL

Data Format Frame Rate Adjust Setting LSB
FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]

RSVD

Reserved

COMJ

Common Control J

Bit[7:3]:

Reserved

Bit[2]:

AEC Band Filter Enable

Bit[1:0]:

Reserved

2E-5F

RSVD

Reserved

SPCB

Signal Process Control B

Bit[7]:

AGC 1.5x Multiplier (Pre-amplifier) Enable

Bit[6:0]:

Reserved

61-6B

RSVD

Reserved

RMCO

Color Matrix RGB Crosstalk Compensation R Channel

Note: This function is not available on the B&W OV7141.

GMCO

Color Matrix RGB Crosstalk Compensation G Channel

Note: This function is not available on the B&W OV7141.

BMCO

Color Matrix RGB Crosstalk Compensation B Channel

Note: This function is not available on the B&W OV7141.

6F-70

RSVD

Reserved

COML

Common Mode Control L

Bit[7]:

Reserved

Bit[6]:

Data Format PCLK output gated by HREF Enable

Bit[5]:

Data Format Output HSYNC on HREF Pin Enable

Bit[4]:

Reserved

Bit[3:2]:

Data Format HSYNC Rising Edge Delay MSB

Bit[1:0]:

Data Format HSYNC Falling Edge Delay MSB

HSDYR

Data Format HSYNC Rising Edge Delay LSB

HSYNCR[9:0] = MSB + LSB = COML[3:2] + HSDYR[7:0]

· Range 000 to 762 pixel delays

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

mni

ision

HSDYF

Data Format HSYNC Falling Edge Delay LSB

HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]

· Range 000 to 762 pixel delays

COMM

Common Mode Control M

Bit[7]:

Reserved

Bit[6:5]:

AGC Maximum Gain Select
00:

+6 dB

01:

+12 dB

10:

+6 dB

11:

+18 dB

Bit[4:0]:

Reserved

COMN

Common Mode Control N

Bit[7]:

Output Format Vertical Flip Enable

Bit[6:0]:

Reserved

COMO

Common Mode Control O

Bit[7:6]:

Reserved

Bit[5]:

Standby Mode Enable

Bit[4:3]:

Reserved

Bit[2]:

SCCB Tri-State Enable VSYNC, HREF and PCLK

Bit[1:0]:

Reserved

77-7D

RSVD

Reserved

AVGY

AEC Digital Y/G Channel Average
(Automatically updated by AGC/AEC, user can only read the values)

AVGR

AEC Digital R/V Channel Average
(Automatically updated by AGC/AEC, user can only read the values)

Note: This function is not available on the B&W OV7141.

AVGB

AEC Digital B/U Channel Average
(Automatically updated by AGC/AEC, user can only read the values)

Note: This function is not available on the B&W OV7141.

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

Table 5

SCCB Register List

Address

(Hex)

Register

Name

Default

(Hex)

R/W

Description

Proprietary to OmniVision Technologies

Version 1.4, March 6, 2003

OV7640/OV7141

CMOS VGA (640 x 480) C

AMERA

HIP

mni

ision

Package Specifications

The OV7640/OV7141 uses a 28-pin plastic package. Refer to

Figure 10

for package information,

Table 6

for package

dimensions, and

Figure 11

for the array center on the chip.

Figure 10 OV7640OV7141 Plastic Package Specifications

Table 6

OV7640/OV7141 Plastic Package Dimensions

Dimensions

Millimeters (mm)

Inches (in.)

Package Size

11.43 + 0.10 SQ

.450 + .004 SQ

Package Height

2.35 + 0.1

.093 + .004

Substrate Height

0.70 + 0.05

.028 + .002

Cavity Size

7.00 + 0.10 SQ

.275 + .004 SQ

Castellation Height

1.07 + 0.05

.042 + .002

Pin #1 Pad Size

0.64 x 2.16

.025 x .085

Pad Size

0.64 x 1.27

.025 x .050

Pad Pitch

1.27 + 0.10

.050 + .004

Package Edge to First Lead Center

1.90 + 0.10

.075 + .004

End-to-End Pad Center-Center

7.62 + 0.10

.300 + .004

Glass Size

10.30 + 0.10 SQ

.406 + .004 SQ

Glass Height

0.55 + 0.05

.022 + .002

.042 ± .002

.028 ± .002

.050 ± .004

.035

MIN.

.025 ± .003

TYP

.075 ± .004

.093 ± .004

.022 ± .002

.001 to .005 TYP

Pin 1
Index

.300 ± .004

.050 TYP

.085
TYP

.009 R REF

TYP

.406

± .004

.028 ± .002

(Metallized)

Chamfer

Pin 1 Index

.275 SQ ± .004

.350 SQ ± .006

.450 SQ ± .004

.012 x 45

.010 x 45

Package Specifications

Version 1.4, March 6, 2003

Proprietary to OmniVision Technologies

mni

ision

Note:

All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site

(http://www.ovt.com

) to obtain the current versions of all

documentation.

OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
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Reproduction of information in OmniVision product documentation and specifications is
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For further information, please feel free to contact OmniVision at

info@ovt.com

OmniVision Technologies, Inc.
Sunnyvale, CA USA
(408) 733-3030

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OV7141

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OV7141