DM9102A
Single Chip Fast Ethernet NIC controller
Final
1
Version: DM9102A-DS-F03
August 28, 2000
General Description
The DM9102A is a fully integrated and cost-effective single
chip Fast Ethernet NIC controller. It is designed with the low
power and high performance process. It is a 3.3V device
with 5V tolerance then it supports 3.3V and 5V signaling.
The DM9102A provides direct interface to the PCI or the
CardBus. It supports bus master capability and fully
complies with PCI 2.2. In media side, The DM9102A
interfaces to the UTP3,4,5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliance with the IEEE 802.3u
Spec. Its auto-negotiation function will automatically
configure the DM9102A to take the maximum advantage of
its abilities. The DM9102A is also support IEEE 802.3x full-
duplex flow control.
The DM9102A supports two types of power-management
mechanisms. The main mechanism is based upon the
OnNow architecture, which is required for PC99. The
alternative mechanism is based upon the remote Wake-On-
LAN mechanism.
Block Diagram
D M A
E E P R O M
Interface
B o o t R O M /
MII Interface
P C I
Interface
TX+/-
RX+/-
M I I M a n a g e m e n t C o n t r o l
& M I I R e g i s t e r
A u t o n e g o t i a t i o n
L E D D r i v e r
P o w e r
M a n a g e m e n t
B l o c k
P M E #
W O L
R X
M a c h i n e
R X
F I F O
T X
F I F O
T X
M a c h i n e
M A C
M I I
N R Z t o N R Z I
N R Z I t o M L T 3
Parallel to
Serial
Scrambler
4 B / 5 B
Encoding
M L T 3 t o N R Z I
N R Z I t o N R Z
Parallel to
Serial
D e -
Scrambler
4 B / 5 B
D e c o d i n g
A E Q
P H Y c e i v e r
DM9102A
Single Chip Fast Ethernet NIC controller
2
Final
Version: DM9102A-DS-F03
August 28, 2000
Table of Contents
General Description ............................................................. 1
Block Diagram...................................................................... 1
Features ............................................................................... 4
Pin Configuration: DM9102A 128pin QFP.......................... 5
Pin Configuration: DM9102A 128pin TQFP ....................... 6
Pin Description ..................................................................... 7
- PCI Bus and CardBus Interface Signals......................... 7
- Boot ROM and EEPROM Interface ................................ 8
T
Multiplex Mode ................................................................ 8
T
Direct Mode.................................................................... 10
- LED Pins......................................................................... 11
- Network Interface ........................................................... 12
- Miscellaneous Pins......................................................... 12
- Power Pins ..................................................................... 13
- Note: LED Mode ............................................................ 13
Register Definition.............................................................. 14
PCI Configuration Registers.......................................... 14
Key to Default..................................................................... 14
T
Identification ID............................................................... 15
T
Command & Status........................................................ 15
T
Revision ID ..................................................................... 17
T
Miscellaneous Function ................................................. 18
T
I/O Base Address........................................................... 18
T
Memory Mapped Base Address.................................... 19
T
Subsystem Identification ................................................ 19
T
CardBus CIS Pointer...................................................... 20
T
Expansion ROM Base Address..................................... 21
T
Capabilities Pointer......................................................... 21
T
Interrupt & Latency Configuration .................................. 22
T
Device Specific Configuration Register......................... 22
T
Power Management Register........................................ 23
T
Power Management Control/Status .............................. 24
Control and Status Register (CR).................................. 25
Key to Default..................................................................... 25
1. System Control Register (CR0)..................................... 26
2. Transmit Descriptor Poll Demand (CR1) ...................... 27
3. Receive Descriptor Poll Demand (CR2) ....................... 27
4. Receive Descriptor Base Address (CR3) ..................... 27
5. Transmit Descriptor Base Address (CR4) .................... 28
6. Network Status Report Register (CR5)......................... 28
7. Network Operation Register (CR6)............................... 30
8. Interrupt Mask Register (CR7)...................................... 32
9. Statistical Counter Register (CR8) ................................ 33
10. PROM & Management Access Register (CR9) ........ 34
11. Programming ROM Address Register (CR10) .......... 35
12. General Purpose Timer Register (CR11)................... 35
13. PHY Status Register (CR12) ...................................... 35
14. Sample Frame Access Register (CR13).................... 36
15. Sample Frame Data Register (CR14) ........................ 36
16. Watching & Jabber Timer Register (CR15)................ 36
CardBus Status Changed Register .............................. 39
1. Function Event Register: (offset 80h)............................ 39
2. Function Event Mask Register: (offset 84h).................. 39
3. Function Present State Register: (offset 88h)............... 39
4. Function Force Event Register: (offset 8Ch) ................ 40
PHY Management Register Set ................................... 41
Key To Default ................................................................... 41
Basic Mode Control Register (BMCR)
- Register 0......................................................................... 42
Basic Mode Status Register (BMSR)
- Register 1......................................................................... 43
PHY ID Identifier Register #1 (PHYIDR1)
- Register 2......................................................................... 44
PHY ID Identifier Register #2 (PHYIDR2)
- Register 3......................................................................... 44
Auto-negotiation Advertisement Register (ANAR)
- Register 4......................................................................... 44
Auto-negotiation Link Partner Ability Register (ANLPAR) -
Register 5........................................................................... 45
Auto-negotiation Expansion Register (ANER)
- Register 6......................................................................... 46
DAVICOM Specified Configuration Register (DSCR)
- Register 10....................................................................... 46
DAVICOM Specified Configuration and Status Register
(DSCSR) - Register 11...................................................... 47
10Base-T Configuration/Status (10BTSCRCSR)
- Register 12....................................................................... 48
Functional Description ....................................................... 49
System Buffer Management ......................................... 49
1. Overview........................................................................ 49
2. Data Structure and Descriptor List ................................ 49
3. Buffer Management: Chain Structure Method.............. 49
5. Descriptor List: Buffer Descriptor Format...................... 49
(a). Receive Descriptor Format......................................... 49
DM9102A
Single Chip Fast Ethernet NIC controller
Final
3
Version: DM9102A-DS-F03
August 28, 2000
(b). Transmit Descriptor Format......................................... 51
Initialization Procedure................................................... 54
Data Buffer Processing Algorithm ..................................... 54
1. Receive Data Buffer Processing ................................... 54
2. Transmit Data Buffer Processing .................................. 55
Network Function........................................................... 56
1. Overview......................................................................... 56
2. Receive Process and State Machine............................ 56
a. Reception Initiation ....................................................... 56
b. Address Recognition.................................................... 56
c. Frame Decapsulation................................................... 56
3. Transmit Process and State Machine........................... 56
a. Transmit Initiation.......................................................... 56
b. Frame Encapsulation................................................... 56
c. Collision......................................................................... 56
4. Physical Layer Overview ............................................... 56
Serial Management Interface ........................................ 57
Power Management ...................................................... 58
1. Overview......................................................................... 58
2. PCI Function Power Management Status .................... 58
3. The Power Management Operation ............................. 58
a. Detect Network Link State Change ............................. 58
b. Active Magic Packet Function...................................... 58
c. Active the Sample Frame Function ............................. 58
Sample Frame Programming Guide............................. 60
Serial ROM Overview........................................................ 61
1. Subsystem ID Block....................................................... 61
2. SROM Version............................................................... 62
3. Controller Count ............................................................. 62
4. Controller_X Information................................................ 62
5. Controller Information Body Pointed By Controller_X Info
Block Offset Item in Controller Information Header....... 62
6. Example of DM9102A SROM Format.......................... 63
External MII/SRL Interface ................................................ 66
The Sharing Pin Table....................................................... 66
Absolute Maximum Ratings .............................................. 68
Operating Conditions......................................................... 68
DC Electrical Characteristics ............................................. 69
AC Electrical Characteristics & Timing Waveforms.......... 70
T
PCI Clock Spec. Timing................................................. 70
T
Other PCI Signals Timing Diagram............................... 70
T
Multiplex Mode Boot ROM Timing................................ 71
T
Direct Mode Boot ROM Timing..................................... 72
T
EEPROM Timing........................................................... 72
T
TP Interface.................................................................... 73
T
Oscillator/Crystal Timing................................................ 73
T
Auto-negotiation and Fast Link Pulse Timing Parameters
........................................................................................ 73
Package Information (128 pin, QFP) ................................ 75
Package Information (128 pin, TQFP).............................. 76
Ordering Information.......................................................... 77
Disclaimer .......................................................................... 77
Company Overview........................................................... 77
Products............................................................................. 77
Contact Windows............................................................... 77
Warning.............................................................................. 77
DM9102A
Single Chip Fast Ethernet NIC controller
4
Final
Version: DM9102A-DS-F03
August 28, 2000
Features
T
Integrated Fast Ethernet MAC, Physical Layer and
transceiver in one chip.
T
128pin QFP/128pin TQFP with CMOS process.
T
+3.3V Power supply with +5V tolerant I/O.
T
Supports PCI and CardBus interfaces.
T
Comply with PCI specification 2.2.
T
PCI clock up to 40MHz.
T
PCI bus master architecture.
T
PCI bus burst mode data transfer.
T
Two large independent FIFO; receive FIFO & transmit
FIFO.
T
Up to 256K bytes Boot EPROM or Flash interface.
T
EEPROM 93C46 interface supports node ID accesses
configuration information and user define message.
T
Node address auto-load and reload.
T
Comply with IEEE 802.3u 100Base-TX and 802.3
10Base-T.
T
Comply with IEEE 802.3u auto-negotiation protocol for
automatic link type selection.
T
Full Duplex/Half Duplex capability.
T
Support IEEE 802.3x Full Duplex Flow Control
T
VLAN support.
T
Comply with ACPI and PCI Bus Power Management.
T
Supports the MII (Media Independent Interface).
T
Supports
Wake-On-LAN
function
and remote wake-up
(Magic packet, Link Change and Microsoft
wake-up
frame).
T
Supports 4 Wake-On-LAN (WOL) signals (active high
pulse, active low pulse, active high , active low ).
T
High performance 100Mbps clock generator and data
recovery circuit.
T
Digital clock recovery circuit using advanced digital
algorithm to reduce jitter.
T
Adaptive
equalization circuit and Baseline wandering
restoration circuit for 100Mbps receiver.
T
Provides Loopback mode for easy system diagnostics.
DM9102A
Single Chip Fast Ethernet NIC controller
Final
5
Version: DM9102A-DS-F03
August 28, 2000
Pin Configuration : 128 pin QFP
11
DM9102A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
60
59
58
57
56
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
90
91
92
93
94
95
96
97
98
99
10
0
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
55
54
53
52
51
61
81
82
83
84
85
86
87
88
89
INT#
RST#
DV
DD
GNT#
REQ#
PCICLK
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD
2
4
C
BE3
#
DG
ND
I
D
SEL
AD
2
3
AD
2
1
AD
2
0
AD
1
9
AD
1
8
AD
1
7
AD
1
6
C
BE2
#
AD
2
2
F
R
AM
E#
ST
O
P
#
I
RDY
#
T
RDY
#
D
EVSEL
#
S
E
RR#
P
E
RR#
CBE0#
BG
R
ESG
BG
R
E
S
DV
DD
X1
/
O
SC
X2
DG
ND
L
I
N
K&AC
T
#
FD
X
#
SPEED
1
0
0
#
SPEED
1
0
#
BPA0
/
W
M
O
D
E
2
BPA1
/
P
C
I
M
O
D
E
#
EED
I
EED
O
EEC
K
EEC
S
SEL
R
O
M
NC
NC
NC
BPAD
4
BPAD
5
BPAD
6
BPAD
7
/
L
E
D
M
O
D
E
BPC
S#
BPAD1
BPAD0
BPAD2
BPAD
3
AD0
AD1
AD2
AD6
AD7
AD5
AD3
T
EST
2
AD4
AD9
AD10
AD11
DVDD
AD13
AD14
AD
1
5
AD12
AD8
C
BE1
#
PAR
(M
A1
0
/
L
I
N
K&AC
T
#
)
(M
A1
1
/
F
D
X
#
)
(M
A1
2
/
SPEED
1
0
0
#
)
(M
A1
3
/
SPEED
1
0
#
)
(MD0/EEDI)
(MD1)
(MD2)
(M
D
3
)
(M
D
4
)
(M
D
5
)
(M
D
6
)
(
M
D7
/
L
E
D
M
O
DE
)
(R
O
M
C
S
)
(M
A0
/
W
M
O
D
E
)
(
M
A
1
/
P
CI
M
O
DE
#
)
(M
A2
)
(M
A3
/
EED
O
)
(M
A4
/
EEC
K)
(M
A5
)
(M
A6
/
SEL
R
O
M
)
(M
A7
)
(M
A8
)
(M
A9
)
DV
DD
DV
DD
DG
ND
DG
ND
DV
DD
DV
DD
DG
ND
DG
ND
27
DVDD
DVDD
DGND
DVDD
DGND
DV
DD
W
O
L
/
CS
T
S
CHG
MA
1
6
10
2
10
1
MA
1
5
MA
1
4
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
127
128
126
DGND
DVDD
ISOLATE#
AVDD
RXI+
RXI-
AGND
TXO+
TXO-
AVDD
AGND
AVDD
NC
NC
W
O
L
/
CS
T
S
CHG
NC
PME#
CL
O
C
K
RUN#
T
EST
1
AVDD
DGND
NC
DV
DD
DG
ND
SU
BG
N
D
DG
ND
DV
DD
DG
ND
DV
DD
DG
ND
DG
ND
MA
1
7
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