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http://www.DigitalCoreDesign.com
are trademarks of their respective owners.
http://www.dcd.pl
Copyright 1999-2003 DCD Digital Core Design. All Rights Reserved.
8-bit FAST Microcontrollers Family
ver 2.08
O V E R V I E W
Document contains brief description of
DF6811 core functionality. The DF6811 is a
advanced 8-bit MCU IP Core with highly so-
phisticated, on chip peripheral capabilities.
DF6811 soft core is binary-compatible with the
industry standard 68HC11 8-bit microcontrol-
ler and can achieve a performance
45-100
million instructions
per second. DF6811 has
FAST architecture that is 3.8 times faster
compared to original implementation. Core in
standard configuration has integrated on chip
major peripheral function.
There are two serial interfaces: an asynchro-
nous serial communications interface (SCI)
and a separate synchronous serial peripheral
interface (SPI).
The main 16-bit, free-running timer system
has implemented three input capture lines,
five output-compare lines, and a real-time in-
terrupt function.
An 8-bit pulse accumulator subsystem can
count external events or measure external
periods.
Self-monitoring circuitry is included on-chip to
protect against system errors. A computer
operating properly (COP) watchdog system
protects against software failures. An illegal
opcode detection circuit provides a non-
maskable interrupt if illegal opcode is de-
tected.
Two software-controlled power-saving modes,
WAIT and STOP, are available to conserve
additional power. These modes make the
DF6811 IP Core especially attractive for
automotive and battery-driven applications.
The DF6811 have built in the development
support features designed into DF6811. The
LIR signal is intended as a debugging aid.
This signal is driven to active low for the first
bus cycle of each new instruction, making it
easy to reverse assemble (disassemble) in-
structions from the display of a logic analyzer.
DF6811 is
fully customizable
, which means
it is delivered in the exact configuration to
meet users requirements.
There is no need to
pay extra for not used features and wasted
silicon.
It includes
fully automated testbench
with
complete set of tests
allowing easy
package validation at each stage of SoC de-
sign flow.
C P U F E A T U R E S
FAST architecture, 3,8 times faster than
the original implementation
Software compatible with industry standard
68HC11
10 times faster multiplication
16 times faster division
64 bytes of remapped System Function
Registers space (SFRs)
Up to 16M bytes of Data Memory
De-multiplexed Address/Data Bus to allow
easy connection to memory
Two power saving modes: STOP, WAI
All trademarks mentioned in this document
http://www.DigitalCoreDesign.com
are trademarks of their respective owners.
http://www.dcd.pl
Copyright 1999-2003 DCD Digital Core Design. All Rights Reserved.
User programmable External Data Memory
Write and Read pulses between 1 to 8
clock periods
Fully synthesizable, static synchronous
design with no internal tri-states
No internal reset generator or gated clock
Scan test ready
Technology independent HDL source code
Core can be fully customized
D E S I G N F E A T U R E S
O
NE GLOBAL SYSTEM CLOCK
S
YNCHRONOUS RESET
The DF6811 has 3 reset vectors
sources, which easy identify a cause of
system reset.
A
LL ASYNCHRONOUS INPUT SIGNALS ARE
SYNCHRONIZED BEFORE INTERNAL USE
D
ATA
M
EMORY
:
The DF6811 can address up to 16M
bytes of Data Memory via the function in-
terconnect signals. The 64 bytes of Data
Memory in every 64k page is reserved for
the Function Registers. Extra DPP (Data
Page Pointer) register is used for segments
swapping. Data Memory can be imple-
mented as synchronous or asynchronous.
P E R I P H E R A L S
The peripherals listed below are not imple-
mented in standard configuration of DF6811.
They can be integrated in Core as a option.
Four 8-bit I/O Ports
Interrupt Controller
20 interrupt sources
17 priority levels
Dedicated Interrupt vector for each interrupt
source
Main16-bit timer/counter system
16 bit free running counter
Four stage programmable prescaller
Timer clocked by internal source
Real Time Interrupt
16-bit Compare/Capture Unit
Three independent input-capture functions
Five output-compare channels
Events capturing
Pulses generation
Digital signals generation
Gated timers
Sophisticated comparator
Pulse width modulation
Pulse width measuring
8-bit Pulse accumulator
Two major modes of operation
Simple event counter
Gated time accumulation
Clocked by internal source or external pin
Full-duplex UART - SCI
Standard Nonreturn to Zero format (NRZ)
8 or 9 bit data transfer
Integrated baud rate generator
Enhanced receiver data sampling technique
Noise, Overrun and Framing error detection
IDLE and BREAK characters generation
Wake-up block to recognize UART wake-up
from IDLE condition
Three SCI related interrupts
SPI Master and Slave Serial Peripheral
Interface
Supports speeds up of system clock
Mode fault error
Write collision error
Software selectable polarity and phase of se-
rial clock SCK
System errors detection
Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
Interrupt generation
All trademarks mentioned in this document
http://www.DigitalCoreDesign.com
are trademarks of their respective owners.
http://www.dcd.pl
Copyright 1999-2003 DCD Digital Core Design. All Rights Reserved.
D E L I V E R A B L E S
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environ-
ment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
C O N F I G U R A T I O N
The following parameters of the DF6811 core
can be easy adjusted to requirements of
dedicated application and technology. Con-
figuration of the core can be prepared by ef-
fortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
- 64
kB
Data Memory size
- 16
MB
- used
(0-7)
Data Memory wait-states
- unused
- used
Power saving STOP mode
- unused
- used
WATCHDOG Timer
- unused
- used
Timer system
- unused
- used
Compare Capture channels
- unused
- used
Pulse Accumulator
- unused
- used
PORTS A, B, C, D
- unused
- used
SCI UART Interface
- unused
- used
SPI Interface
- unused
- used
Support for IDIV Instruction
- unused
- used
Support for FDIV Instruction
- unused
- used
Support for MUL Instruction
- unused
- used
Support for DAA Instruction
- unused
L I C E N S I N G
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design
license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year
licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except
One Year
license where time of
use is limited to 12 months.
Single Design license for
VHDL, Verilog source code called HDL
Source
Encrypted,or plain text EDIF called Netlist
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source
Netlist
Upgrade from
HDL Source to Netlist
Single Design to Unlimited Designs
All trademarks mentioned in this document
http://www.DigitalCoreDesign.com
are trademarks of their respective owners.
http://www.dcd.pl
Copyright 1999-2003 DCD Digital Core Design. All Rights Reserved.
P I N S D E S C R I P T I O N
PIN
ACTIVE TYPE
DESCRIPTION
clk
-
input Global system clock
rst
Low
input Global system reset
datai[7:0]
-
input External memory bus input
ufrdatai[7:0]
-
input UFRs data bus input
por
Low
input Power on reset vector fetch
copi
Low
input COP timeout vector fetch
cmf
Low
input Clock monitor fail vector fetch
datai[7:0]
-
input External memory bus input
ufrdatai[7:0]
-
input UFRs data bus input
irq
*
input Interrupt input
xirq
Low
input Non-maskable interrupt input
portai[7:0]
-
input Port A input
portbi[7:0]
-
input Port B input
portci[7:0]
-
input Port C input
portdi[7:0]
-
input Port D input
cap1,2,3
Low
input Capture inputs
pai
*
input Pulse accumulator input
rxd
Low
input SCI receiver data input
si
High
input SPI slave input
mi
High
input SPI master input
scki
*
input SPI clock input
ss
Low
input SPI slave select
datao[7:0]
-
output Data memory & UFR bus output
addr[23:0]
-
output Data memory & FR address bus
ramwe
Low
output Memory write enable
ramoe
Low
output Memory output enable
ufrwe
Low
output UFRs write enable
ufroe
Low
output UFRs output enable
lir
Low
output Load instruction register
halt
High
output Halt clock system (STOP inst.)
cme
High
output Clock monitor enable
copo
Low
output WATCHDOG timeout output
cmp1,2,3,4,5
*
output Compare outputs
cmp1z,2,3,4,5
High
output Disconnect output compare
portxo[7:0]
-
output Port A, B, C, D output
ddrx[7:0]
-
output Port A, B,C,D data direction
control
cmp1,2,3,4,5
*
output Compare outputs
cmp1z,2,3,4,5
High
output Disconnect output compare
txd
Low
output SCI transmitter data output
so
High
output SPI slave output
mo
High
output SPI master output
scko
*
output SPI clock output
sckz
High
output Disconnect SPI clock output
* Kind of activity is configurable
S Y M B O L
ramwe
ramoe
ufrwe
ufroe
portao(7:0)
portdo(7:0)
portco(7:0)
portbo(7:0)
portai(7:0)
portbi(7:0)
portci(7:0)
portdi(7:0)
datai(7:0)
ufrdatai(7:0)
irq
xirq
pai
cap1
cap2
cap3
clk
rst
rxd
datao(7:0)
addr(23:0)
txd
si
mi
so
mo
scki
scko
sckz
ss
por
copi
cmf
halt
cme
ddra(7:0)
ddrd(7:0)
ddrc(7:0)
ddrb(7:0)
cmp1z
cmp2z
cmp3z
cmp4z
cmp5z
cmp1
cmp2
cmp3
cmp4
cmp5
lir
copo
B L O C K D I A G R A M
Control Unit
- Performs the core synchroniza-
tion and data flow control. This module man-
ages execution of all instructions. The Control
Unit also manages execution of STOP instruc-
tion and waking-up the processor from the
STOP mode.
Opcode Decoder
- Performs an instruction
opcode decoding and the control functions for
all other blocks
.
All trademarks mentioned in this document
http://www.DigitalCoreDesign.com
are trademarks of their respective owners.
http://www.dcd.pl
Copyright 1999-2003 DCD Digital Core Design. All Rights Reserved.
ALU
- Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(A, B), Condition Code Register (CCREG),
Index registers X, Y and related logic such as
arithmetic unit, logic unit, multiplier and di-
vider.
portao(7:0)
portdo(7:0)
portco(7:0)
portbo(7:0)
datai(7:0)
clk
rst
datao(7:0)
cap1
cap2
cap3
RAM
&
SFR
Control
I/O
Ports
Opcode
Decoder
Control
Unit
Interrupt
Controller
Timer
with
Compare /
Capture
Unit
SCI Unit
SPI Unit
irq
por
cmp1
cmp2
cmp3
cmp4
cmp5
cmp1z
cmp2z
cmp3z
cmp4z
cmp5z
txd
rxd
mo
so
si
scki
mi
scko
sckz
cme
xirq
ramoe
ramwe
addr(23:0)
ss
halt
cmf
copi
portai(7:0)
portdi(7:0)
portci(7:0)
portbi(7:0)
lir
ddra(7:0)
ddrd(7:0)
ddrc(7:0)
ddrb(7:0)
Watchdog
Timer
Pulse
Accumulator
pai
copo
ALU
ufroe
ufrwe
RAM & SFR Controller
- Data Memory &
SFR (Special Function Register) interface
controls access into the internal and external
program and data memories and special reg-
isters. It contains Stack Pointer (SP) register,
INIT register (INIT), Data Page Pointer (DPP),
Stretch register (ST) and related logic.
Interrupt Controller
- DF6811 extended IC
has implemented 17-level interrupt priority
control. The interrupt requests may come from
external pins (IRQ and XIRQ) as well as from
particular peripherals. The DF6811 peripheral
systems generate maskable interrupts, which
are recognized only if the global interrupt
mask bit (I) in the CCR is cleared. Maskable
interrupts are prioritized according to default
arrangement (look at the table below) estab-
lished during reset. However any one source
may be elevated to the highest maskable pri-
ority position using HPRIO register. When
interrupt condition occurs, an interrupt status
flag is set to indicate the condition. and di-
vider.
Timer, Compare Capture & COP Watchdog
- This timer system is based on a free-running
16-bit counter with a 4-stage programmable
prescaler. A timer overflow function allows
software to extend the timing capability of the
system beyond the 16-bit range of the coun-
ter. Three independent input-capture functions
are used to automatically record the time
when a selected transition is detected at a
respective timer input pin. Five output-
compare functions are included for generating
output signals or for timing software delays.
Since the input-capture and output-compare
functions may not be familiar to all users,
these concepts are explained in greater detail.
A programmable periodic interrupt circuit
called RTI is tapped off of the main 16-bit
timer counter. Software can select one of four
rates for the RTI, which is most commonly
used to pace the execution of software rou-
tines. The COP watchdog function is loosely
related to the main timer in that the clock input
to the COP system (clk*2
17
) is tapped off the
free-running counter chain.
The timer subsystem involves more registers
and control bits than any other subsystem on
the MCU. Each of the three input-capture
functions has its own 16-bit time capture latch
(input-capture register) and each of the five
output-compare functions has its own 16-bit
compare register. All timer functions, including
the timer overflow and RTI, have their own
interrupt controls and separate interrupt vec-
tors. Additional control bits permit software to
control the edge(s) that trigger each input-
capture function and the automatic actions
that result from output-compare functions.
Although hardwired logic is included to auto-
mate many timer activities, this timer architec-
ture is essentially a software-oriented system.
This structure is easily adaptable to a very
wide range of applications although it is not as
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